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9cdcbc9f67
Set core_get/put ops for CNL/ICL platforms. These platforms do not support enabling/disabling secondary cores dynamically. So skip sending the IPC to power off the cores in the core_put op. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Link: https://lore.kernel.org/r/20211119192621.4096077-6-kai.vehmanen@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
380 lines
10 KiB
C
380 lines
10 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Cannonlake.
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*/
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#include "../ops.h"
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#include "hda.h"
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#include "hda-ipc.h"
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#include "../sof-audio.h"
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static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
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irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 hipci;
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u32 hipcida;
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u32 hipctdr;
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u32 hipctdd;
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u32 msg;
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u32 msg_ext;
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bool ipc_irq = false;
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hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
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hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
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hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
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hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
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/* reply message from DSP */
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if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
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msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
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msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
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dev_vdbg(sdev->dev,
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"ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
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msg, msg_ext);
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/* mask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE, 0);
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spin_lock_irq(&sdev->ipc_lock);
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/* handle immediate reply from DSP core */
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hda_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, msg);
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cnl_ipc_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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ipc_irq = true;
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}
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/* new message from DSP */
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if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
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msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
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msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
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dev_vdbg(sdev->dev,
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"ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
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msg, msg_ext);
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/* handle messages from DSP */
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if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
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SOF_IPC_PANIC_MAGIC) {
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snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
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} else {
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snd_sof_ipc_msgs_rx(sdev);
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}
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cnl_ipc_host_done(sdev);
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ipc_irq = true;
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}
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if (!ipc_irq) {
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/*
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* This interrupt is not shared so no need to return IRQ_NONE.
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*/
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dev_dbg_ratelimited(sdev->dev,
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"nothing to do in IPC IRQ thread\n");
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}
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return IRQ_HANDLED;
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}
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
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{
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/*
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* clear busy interrupt to tell dsp controller this
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* interrupt has been accepted, not trigger it again
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDR,
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CNL_DSP_REG_HIPCTDR_BUSY,
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CNL_DSP_REG_HIPCTDR_BUSY);
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/*
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* set done bit to ack dsp the msg has been
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* processed and send reply msg to dsp
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDA,
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CNL_DSP_REG_HIPCTDA_DONE,
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CNL_DSP_REG_HIPCTDA_DONE);
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}
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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/*
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* set DONE bit - tell DSP we have received the reply msg
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* from DSP, and processed it, don't send more reply to host
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCIDA,
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CNL_DSP_REG_HIPCIDA_DONE,
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CNL_DSP_REG_HIPCIDA_DONE);
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/* unmask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE,
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CNL_DSP_REG_HIPCCTL_DONE);
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}
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static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
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u32 *dr, u32 *dd)
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{
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struct sof_ipc_pm_gate *pm_gate;
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if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
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pm_gate = msg->msg_data;
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/* send the compact message via the primary register */
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*dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
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/* send payload via the extended data register */
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*dd = pm_gate->flags;
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return true;
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}
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return false;
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}
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int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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struct sof_ipc_cmd_hdr *hdr;
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u32 dr = 0;
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u32 dd = 0;
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/*
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* Currently the only compact IPC supported is the PM_GATE
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* IPC which is used for transitioning the DSP between the
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* D0I0 and D0I3 states. And these are sent only during the
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* set_power_state() op. Therefore, there will never be a case
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* that a compact IPC results in the DSP exiting D0I3 without
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* the host and FW being in sync.
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*/
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if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
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/* send the message via IPC registers */
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
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dd);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY | dr);
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return 0;
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}
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/* send the message via mailbox */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY);
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hdr = msg->msg_data;
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/*
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* Use mod_delayed_work() to schedule the delayed work
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* to avoid scheduling multiple workqueue items when
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* IPCs are sent at a high-rate. mod_delayed_work()
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* modifies the timer if the work is pending.
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* Also, a new delayed work should not be queued after the
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* CTX_SAVE IPC, which is sent before the DSP enters D3.
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*/
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if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
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mod_delayed_work(system_wq, &hdev->d0i3_work,
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msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
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return 0;
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}
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void cnl_ipc_dump(struct snd_sof_dev *sdev)
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{
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u32 hipcctl;
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u32 hipcida;
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u32 hipctdr;
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hda_ipc_irq_dump(sdev);
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/* read IPC status */
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hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
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hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
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hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
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/* dump the IPC regs */
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/* TODO: parse the raw msg */
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dev_err(sdev->dev,
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"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
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hipcida, hipctdr, hipcctl);
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}
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/* cannonlake ops */
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const struct snd_sof_dsp_ops sof_cnl_ops = {
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/* probe/remove/shutdown */
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.probe = hda_dsp_probe,
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.remove = hda_dsp_remove,
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.shutdown = hda_dsp_shutdown,
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/* Register IO */
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.write = sof_io_write,
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.read = sof_io_read,
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.write64 = sof_io_write64,
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.read64 = sof_io_read64,
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/* Block IO */
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.block_read = sof_block_read,
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.block_write = sof_block_write,
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/* Mailbox IO */
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.mailbox_read = sof_mailbox_read,
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.mailbox_write = sof_mailbox_write,
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/* doorbell */
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.irq_thread = cnl_ipc_irq_thread,
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/* ipc */
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.send_msg = cnl_ipc_send_msg,
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.fw_ready = sof_fw_ready,
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.get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
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.get_window_offset = hda_dsp_ipc_get_window_offset,
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.ipc_msg_data = hda_ipc_msg_data,
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.ipc_pcm_params = hda_ipc_pcm_params,
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/* machine driver */
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.machine_select = hda_machine_select,
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.machine_register = sof_machine_register,
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.machine_unregister = sof_machine_unregister,
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.set_mach_params = hda_set_mach_params,
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/* debug */
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.debug_map = cnl_dsp_debugfs,
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.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
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.dbg_dump = hda_dsp_dump,
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.ipc_dump = cnl_ipc_dump,
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.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
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/* stream callbacks */
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.pcm_open = hda_dsp_pcm_open,
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.pcm_close = hda_dsp_pcm_close,
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.pcm_hw_params = hda_dsp_pcm_hw_params,
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.pcm_hw_free = hda_dsp_stream_hw_free,
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.pcm_trigger = hda_dsp_pcm_trigger,
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.pcm_pointer = hda_dsp_pcm_pointer,
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
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/* probe callbacks */
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.probe_assign = hda_probe_compr_assign,
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.probe_free = hda_probe_compr_free,
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.probe_set_params = hda_probe_compr_set_params,
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.probe_trigger = hda_probe_compr_trigger,
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.probe_pointer = hda_probe_compr_pointer,
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#endif
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/* firmware loading */
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.load_firmware = snd_sof_load_firmware_raw,
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/* pre/post fw run */
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.pre_fw_run = hda_dsp_pre_fw_run,
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.post_fw_run = hda_dsp_post_fw_run,
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/* parse platform specific extended manifest */
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.parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data,
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/* dsp core power up/down */
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.core_power_up = hda_dsp_enable_core,
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.core_power_down = hda_dsp_core_reset_power_down,
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.core_get = hda_dsp_core_get,
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/* firmware run */
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.run = hda_dsp_cl_boot_firmware,
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/* trace callback */
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.trace_init = hda_dsp_trace_init,
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.trace_release = hda_dsp_trace_release,
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.trace_trigger = hda_dsp_trace_trigger,
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/* DAI drivers */
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.drv = skl_dai,
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.num_drv = SOF_SKL_NUM_DAIS,
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/* PM */
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.suspend = hda_dsp_suspend,
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.resume = hda_dsp_resume,
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.runtime_suspend = hda_dsp_runtime_suspend,
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.runtime_resume = hda_dsp_runtime_resume,
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.runtime_idle = hda_dsp_runtime_idle,
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.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
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.set_power_state = hda_dsp_set_power_state,
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/* ALSA HW info flags */
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.hw_info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
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.dsp_arch_ops = &sof_xtensa_arch_ops,
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};
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EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc cnl_chip_info = {
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/* Cannonlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.host_managed_cores_mask = GENMASK(3, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = CNL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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.sdw_shim_base = SDW_SHIM_BASE,
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.sdw_alh_base = SDW_ALH_BASE,
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.check_sdw_irq = hda_common_check_sdw_irq,
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};
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EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc jsl_chip_info = {
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/* Jasperlake */
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.cores_num = 2,
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.init_core_mask = 1,
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.host_managed_cores_mask = GENMASK(1, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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.sdw_shim_base = SDW_SHIM_BASE,
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.sdw_alh_base = SDW_ALH_BASE,
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.check_sdw_irq = hda_common_check_sdw_irq,
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};
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EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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