mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-12 05:24:12 +08:00
7e961c12be
This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
26 lines
907 B
Makefile
26 lines
907 B
Makefile
#
|
|
# Makefile for the fpga framework and fpga manager drivers.
|
|
#
|
|
|
|
# Core FPGA Manager Framework
|
|
obj-$(CONFIG_FPGA) += fpga-mgr.o
|
|
|
|
# FPGA Manager Drivers
|
|
obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
|
|
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
|
|
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
|
|
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
|
|
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
|
|
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
|
|
|
|
# FPGA Bridge Drivers
|
|
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
|
|
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
|
|
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
|
|
obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
|
|
|
|
# High Level Interfaces
|
|
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
|