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5e72f5dc7e
This board has a Micron MT29F8G08ABACAWP chip which requires a ECC strength of 8/512. Rather than hard coding any particular strength the the nand controller auto-detect the ECC strength based on the ONFI data. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
156 lines
2.3 KiB
Plaintext
156 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Marvell Armada 385 AMC board
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* (DB-88F6820-AMC)
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*
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* Copyright (C) 2017 Allied Telesis Labs
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada 385 AMC";
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compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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ethernet0 = ð0;
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ethernet1 = ð1;
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spi1 = &spi1;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000>; /* 2GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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};
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&uart0 {
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/*
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* Exported on the micro USB connector CON3
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* through an FTDI
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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ð0 {
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pinctrl-names = "default";
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/*
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* The Reference Clock 0 is used to provide a
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* clock to the PHY
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*/
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pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ð2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "sgmii";
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};
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&usb0 {
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status = "okay";
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};
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&mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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phy1: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&nand_controller {
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status = "okay";
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nand@0 {
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reg = <0>;
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label = "pxa3xx_nand-0";
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nand-rb = <0>;
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nand-on-flash-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x00000000 0x40000000>;
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label = "user";
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};
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};
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie1 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x00000000 0x00100000>;
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label = "u-boot";
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};
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partition@100000 {
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reg = <0x00100000 0x00040000>;
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label = "u-boot-env";
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};
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};
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};
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};
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&refclk {
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clock-frequency = <20000000>;
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};
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