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b42990d3bf
The vector lengths used for SME are controlled through a similar set of registers to those for SVE and enumerated using a similar algorithm with some slight differences due to the fact that unlike SVE there are no restrictions on which combinations of vector lengths can be supported nor any mandatory vector lengths which must be implemented. Add a new vector type and implement support for enumerating it. One slightly awkward feature is that we need to read the current vector length using a different instruction (or enter streaming mode which would have the same issue and be higher cost). Rather than add an ops structure we add special cases directly in the otherwise generic vec_probe_vqs() function, this is a bit inelegant but it's the only place where this is an issue. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419112247.711548-10-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
82 lines
1.6 KiB
C
82 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#ifndef __ASM_CPU_H
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#define __ASM_CPU_H
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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/*
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* Records attributes of an individual CPU.
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*/
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struct cpuinfo_32bit {
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u32 reg_id_dfr0;
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u32 reg_id_dfr1;
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u32 reg_id_isar0;
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u32 reg_id_isar1;
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u32 reg_id_isar2;
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u32 reg_id_isar3;
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u32 reg_id_isar4;
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u32 reg_id_isar5;
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u32 reg_id_isar6;
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u32 reg_id_mmfr0;
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u32 reg_id_mmfr1;
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u32 reg_id_mmfr2;
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u32 reg_id_mmfr3;
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u32 reg_id_mmfr4;
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u32 reg_id_mmfr5;
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u32 reg_id_pfr0;
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u32 reg_id_pfr1;
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u32 reg_id_pfr2;
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u32 reg_mvfr0;
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u32 reg_mvfr1;
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u32 reg_mvfr2;
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};
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struct cpuinfo_arm64 {
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struct cpu cpu;
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struct kobject kobj;
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u64 reg_ctr;
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u64 reg_cntfrq;
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u64 reg_dczid;
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u64 reg_midr;
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u64 reg_revidr;
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u64 reg_gmid;
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u64 reg_id_aa64dfr0;
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u64 reg_id_aa64dfr1;
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u64 reg_id_aa64isar0;
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u64 reg_id_aa64isar1;
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u64 reg_id_aa64isar2;
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u64 reg_id_aa64mmfr0;
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u64 reg_id_aa64mmfr1;
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u64 reg_id_aa64mmfr2;
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u64 reg_id_aa64pfr0;
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u64 reg_id_aa64pfr1;
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u64 reg_id_aa64zfr0;
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u64 reg_id_aa64smfr0;
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struct cpuinfo_32bit aarch32;
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/* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */
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u64 reg_zcr;
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/* pseudo-SMCR for recording maximum SMCR_EL1 LEN value: */
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u64 reg_smcr;
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};
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DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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void cpuinfo_store_cpu(void);
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void __init cpuinfo_store_boot_cpu(void);
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void __init init_cpu_features(struct cpuinfo_arm64 *info);
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void update_cpu_features(int cpu, struct cpuinfo_arm64 *info,
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struct cpuinfo_arm64 *boot);
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#endif /* __ASM_CPU_H */
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