Vincent Wan 9b8ffea6ef mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data ... SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms Signed-off-by: Vincent Wan <vincent.wan@amd.com> Signed-off-by: Wan Zongshun <mcuos.com@gmail.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Tested-by: Vikram B <vikram.b@amd.com> Tested-by: Raghavendra Swamy <raghavendra.swamy@amd.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>		2014-11-26 14:30:28 +01:00
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card	mmc: mmc_test: Extend "Badly aligned" tests for 8-byte alignment	2014-11-10 12:40:54 +01:00
core	mmc: core: use mmc_send_status to check hw_reset	2014-11-10 12:40:56 +01:00
host	mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data	2014-11-26 14:30:28 +01:00
Kconfig	mmc: explicitly mention SDIO support in Kconfig	2008-10-12 11:04:36 +02:00
Makefile	mmc: sdhci-pci: add platform data	2012-01-11 23:58:47 -05:00