korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-29 22:14:41 +08:00
Code Issues Packages Projects Releases Wiki Activity
9b51878863
linux/drivers/clk/qcom/camcc-sm8450.c
Vladimir Zapolskiy 6082037fe6 clk: qcom: add camera clock controller driver for SM8450 SoC 
Add  camera clock controller driver found on Qualcomm SM8450 SoC.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org
2022-07-06 15:20:59 -05:00

2857 lines
75 KiB
C
Raw Blame History

// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_IFACE,
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK
};
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL0_OUT_MAIN,
P_CAM_CC_PLL0_OUT_ODD,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_EVEN,
P_CAM_CC_PLL2_OUT_MAIN,
P_CAM_CC_PLL3_OUT_EVEN,
P_CAM_CC_PLL4_OUT_EVEN,
P_CAM_CC_PLL5_OUT_EVEN,
P_CAM_CC_PLL6_OUT_EVEN,
P_CAM_CC_PLL7_OUT_EVEN,
P_CAM_CC_PLL8_OUT_EVEN,
P_SLEEP_CLK,
};
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct pll_vco rivian_evo_vco[] = {
{ 864000000, 1056000000, 0 },
};
static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct alpha_pll_config cam_cc_pll0_config = {
.l = 0x3e,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00008400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
{ 0x2, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
.offset = 0x0,
.post_div_shift = 14,
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0_out_odd",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll1_config = {
.l = 0x25,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll1",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll1_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll2_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x90008820,
.config_ctl_hi_val = 0x00890263,
.config_ctl_hi1_val = 0x00000217,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = rivian_evo_vco,
.num_vco = ARRAY_SIZE(rivian_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll2",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_rivian_evo_ops,
},
},
};
static const struct alpha_pll_config cam_cc_pll3_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll3",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.offset = 0x3000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll3_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll4_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll4",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
.offset = 0x4000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll4_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll4_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll5_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll5 = {
.offset = 0x5000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll5",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
.offset = 0x5000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll5_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll5_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll5.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll6_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll6 = {
.offset = 0x6000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll6",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
.offset = 0x6000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll6_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll7_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll7 = {
.offset = 0x7000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll7",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
.offset = 0x7000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll7_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll7_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll7.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll8_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll8 = {
.offset = 0x8000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll8",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
.offset = 0x8000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll8_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll8_out_even",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_pll8.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL8_OUT_EVEN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll8_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll2.clkr.hw },
{ .hw = &cam_cc_pll2.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll5_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
};
static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll7_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_8[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_8[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map cam_cc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
{ .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x10050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
.cmd_rcgr = 0x13194,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0x1312c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.cmd_rcgr = 0x13148,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0x1104c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x150e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x15104,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x15124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x1514c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
.cmd_rcgr = 0x1516c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi4phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
.cmd_rcgr = 0x1518c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi5phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csid_clk_src = {
.cmd_rcgr = 0x13174,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csid_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x10018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0x13108,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0x11018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0x12018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_2_clk_src = {
.cmd_rcgr = 0x12064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.cmd_rcgr = 0x13000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0x13024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
.cmd_rcgr = 0x1008c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0x130dc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0x15000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0x1501c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0x15038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0x15054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.cmd_rcgr = 0x15070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
.cmd_rcgr = 0x1508c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk5_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk6_clk_src = {
.cmd_rcgr = 0x150a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk6_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk7_clk_src = {
.cmd_rcgr = 0x150c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk7_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
.cmd_rcgr = 0x131bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
.cmd_rcgr = 0x13064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_6,
.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_clk_src",
.parent_data = cam_cc_parent_data_6,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
.cmd_rcgr = 0x130ac,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_7,
.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_clk_src",
.parent_data = cam_cc_parent_data_7,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sleep_clk_src = {
.cmd_rcgr = 0x13210,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_8,
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sleep_clk_src",
.parent_data = cam_cc_parent_data_8,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x10034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_xo_clk_src = {
.cmd_rcgr = 0x131f4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_9,
.freq_tbl = ftbl_cam_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_xo_clk_src",
.parent_data = cam_cc_parent_data_9_ao,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch cam_cc_gdsc_clk = {
.halt_reg = 0x1320c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1320c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_gdsc_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x1004c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1004c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x10068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_fast_ahb_clk = {
.halt_reg = 0x10030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_clk = {
.halt_reg = 0x131ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
.halt_reg = 0x131b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_dcd_xo_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0x13144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_1_clk = {
.halt_reg = 0x13160,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13160,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_core_ahb_clk = {
.halt_reg = 0x131f0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x131f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_core_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0x13164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_bps_clk = {
.halt_reg = 0x10070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_bps_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
.halt_reg = 0x1316c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1316c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_0_clk = {
.halt_reg = 0x11038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_1_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_2_clk = {
.halt_reg = 0x12084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_2_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_lite_clk = {
.halt_reg = 0x13020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_lite_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
.halt_reg = 0x100ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ipe_nps_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sbi_clk = {
.halt_reg = 0x100ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100ec,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sbi_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_0_clk = {
.halt_reg = 0x13084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_sfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_1_clk = {
.halt_reg = 0x130cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_sfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0x150f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150f8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi0phytimer_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0x1511c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1511c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi1phytimer_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0x1513c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1513c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi2phytimer_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0x15164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi3phytimer_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi4phytimer_clk = {
.halt_reg = 0x15184,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15184,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi4phytimer_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csi4phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi5phytimer_clk = {
.halt_reg = 0x151a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi5phytimer_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csi5phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csid_clk = {
.halt_reg = 0x1318c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1318c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
.halt_reg = 0x15100,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15100,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_csiphy_rx_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0x150fc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150fc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0x15120,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0x15140,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15140,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy2_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0x15168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15168,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy3_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy4_clk = {
.halt_reg = 0x15188,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15188,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy4_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy5_clk = {
.halt_reg = 0x151a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy5_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_ahb_clk = {
.halt_reg = 0x13128,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13128,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0x13120,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0x11030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_dsp_clk = {
.halt_reg = 0x1103c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1103c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_dsp_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
.halt_reg = 0x11048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0x12030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_dsp_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1203c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_dsp_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
.halt_reg = 0x12048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_clk = {
.halt_reg = 0x1207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1207c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_dsp_clk = {
.halt_reg = 0x12088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_dsp_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
.halt_reg = 0x12094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
.halt_reg = 0x13048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_clk = {
.halt_reg = 0x13018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.halt_reg = 0x13044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_csid_clk = {
.halt_reg = 0x1303c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1303c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_csid_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
.halt_reg = 0x100c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_clk = {
.halt_reg = 0x100a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
.halt_reg = 0x100c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_pps_clk = {
.halt_reg = 0x100b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_pps_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
.halt_reg = 0x100c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_pps_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0x130f4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130f4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0x15018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0x15034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0x15050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk2_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0x1506c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1506c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk3_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk4_clk = {
.halt_reg = 0x15088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk4_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk5_clk = {
.halt_reg = 0x150a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk5_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk6_clk = {
.halt_reg = 0x150c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk6_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk7_clk = {
.halt_reg = 0x150dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk7_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_mclk7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_clk = {
.halt_reg = 0x131d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_qdss_debug_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
.halt_reg = 0x131d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_xo_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_ahb_clk = {
.halt_reg = 0x100f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_clk = {
.halt_reg = 0x100e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_clk = {
.halt_reg = 0x1307c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1307c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_sfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
.halt_reg = 0x13090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_clk = {
.halt_reg = 0x130c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130c4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_sfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
.halt_reg = 0x130d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_fast_ahb_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sleep_clk = {
.halt_reg = 0x13228,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13228,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sleep_clk",
.parent_data = &(const struct clk_parent_data) {
.hw = &cam_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *cam_cc_sm8450_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
};
static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
[CAM_CC_BPS_BCR] = { 0x10000 },
[CAM_CC_ICP_BCR] = { 0x13104 },
[CAM_CC_IFE_0_BCR] = { 0x11000 },
[CAM_CC_IFE_1_BCR] = { 0x12000 },
[CAM_CC_IFE_2_BCR] = { 0x1204c },
[CAM_CC_IPE_0_BCR] = { 0x10074 },
[CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 },
[CAM_CC_SBI_BCR] = { 0x100cc },
[CAM_CC_SFE_0_BCR] = { 0x1304c },
[CAM_CC_SFE_1_BCR] = { 0x13094 },
};
static const struct regmap_config cam_cc_sm8450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1601c,
.fast_io = true,
};
static struct gdsc titan_top_gdsc;
static struct gdsc bps_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "bps_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x10078,
.pd = {
.name = "ipe_0_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sbi_gdsc = {
.gdscr = 0x100d0,
.pd = {
.name = "sbi_gdsc",
},
.flags = POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_0_gdsc = {
.gdscr = 0x11004,
.pd = {
.name = "ife_0_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_1_gdsc = {
.gdscr = 0x12004,
.pd = {
.name = "ife_1_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_2_gdsc = {
.gdscr = 0x12050,
.pd = {
.name = "ife_2_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sfe_0_gdsc = {
.gdscr = 0x13050,
.pd = {
.name = "sfe_0_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sfe_1_gdsc = {
.gdscr = 0x13098,
.pd = {
.name = "sfe_1_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc titan_top_gdsc = {
.gdscr = 0x131dc,
.pd = {
.name = "titan_top_gdsc",
},
.flags = POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc *cam_cc_sm8450_gdscs[] = {
[BPS_GDSC] = &bps_gdsc,
[IPE_0_GDSC] = &ipe_0_gdsc,
[SBI_GDSC] = &sbi_gdsc,
[IFE_0_GDSC] = &ife_0_gdsc,
[IFE_1_GDSC] = &ife_1_gdsc,
[IFE_2_GDSC] = &ife_2_gdsc,
[SFE_0_GDSC] = &sfe_0_gdsc,
[SFE_1_GDSC] = &sfe_1_gdsc,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static const struct qcom_cc_desc cam_cc_sm8450_desc = {
.config = &cam_cc_sm8450_regmap_config,
.clks = cam_cc_sm8450_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks),
.resets = cam_cc_sm8450_resets,
.num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
.gdscs = cam_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
};
static const struct of_device_id cam_cc_sm8450_match_table[] = {
{ .compatible = "qcom,sm8450-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
static int cam_cc_sm8450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
}
static struct platform_driver cam_cc_sm8450_driver = {
.probe = cam_cc_sm8450_probe,
.driver = {
.name = "camcc-sm8450",
.of_match_table = cam_cc_sm8450_match_table,
},
};
module_platform_driver(cam_cc_sm8450_driver);
MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
MODULE_LICENSE("GPL");
Reference in New Issue View Git Blame Copy Permalink