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48f15e94f5
Acking interrupts are done differently between on v2 and v3, so add an extra attribute to the pingroup struct to let the platform definitions control this. Also make sure to start dual edge detection by detecting the rising edge. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
121 lines
4.5 KiB
C
121 lines
4.5 KiB
C
/*
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* Copyright (c) 2013, Sony Mobile Communications AB.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PINCTRL_MSM_H__
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#define __PINCTRL_MSM_H__
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struct pinctrl_pin_desc;
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/**
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* struct msm_function - a pinmux function
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* @name: Name of the pinmux function.
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* @groups: List of pingroups for this function.
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* @ngroups: Number of entries in @groups.
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*/
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struct msm_function {
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const char *name;
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const char * const *groups;
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unsigned ngroups;
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};
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/**
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* struct msm_pingroup - Qualcomm pingroup definition
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* @name: Name of the pingroup.
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* @pins: A list of pins assigned to this pingroup.
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* @npins: Number of entries in @pins.
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* @funcs: A list of pinmux functions that can be selected for
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* this group. The index of the selected function is used
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* for programming the function selector.
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* Entries should be indices into the groups list of the
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* struct msm_pinctrl_soc_data.
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* @ctl_reg: Offset of the register holding control bits for this group.
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* @io_reg: Offset of the register holding input/output bits for this group.
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* @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
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* @intr_status_reg: Offset of the register holding the status bits for this group.
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* @intr_target_reg: Offset of the register specifying routing of the interrupts
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* from this group.
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* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
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* @pull_bit: Offset in @ctl_reg for the bias configuration.
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* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
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* @oe_bit: Offset in @ctl_reg for controlling output enable.
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* @in_bit: Offset in @io_reg for the input bit value.
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* @out_bit: Offset in @io_reg for the output bit value.
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* @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
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* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
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* status.
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* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
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* @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
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* @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
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* @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
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* @intr_detection_width: Number of bits used for specifying interrupt type,
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* Should be 2 for SoCs that can detect both edges in hardware,
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* otherwise 1.
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*/
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struct msm_pingroup {
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const char *name;
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const unsigned *pins;
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unsigned npins;
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unsigned funcs[8];
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s16 ctl_reg;
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s16 io_reg;
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s16 intr_cfg_reg;
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s16 intr_status_reg;
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s16 intr_target_reg;
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unsigned mux_bit:5;
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unsigned pull_bit:5;
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unsigned drv_bit:5;
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unsigned oe_bit:5;
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unsigned in_bit:5;
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unsigned out_bit:5;
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unsigned intr_enable_bit:5;
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unsigned intr_status_bit:5;
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unsigned intr_ack_high:1;
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unsigned intr_target_bit:5;
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unsigned intr_raw_status_bit:5;
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unsigned intr_polarity_bit:5;
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unsigned intr_detection_bit:5;
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unsigned intr_detection_width:5;
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};
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/**
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* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
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* @pins: An array describing all pins the pin controller affects.
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* @npins: The number of entries in @pins.
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* @functions: An array describing all mux functions the SoC supports.
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* @nfunctions: The number of entries in @functions.
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* @groups: An array describing all pin groups the pin SoC supports.
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* @ngroups: The numbmer of entries in @groups.
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* @ngpio: The number of pingroups the driver should expose as GPIOs.
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*/
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struct msm_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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unsigned npins;
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const struct msm_function *functions;
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unsigned nfunctions;
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const struct msm_pingroup *groups;
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unsigned ngroups;
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unsigned ngpios;
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};
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int msm_pinctrl_probe(struct platform_device *pdev,
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const struct msm_pinctrl_soc_data *soc_data);
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int msm_pinctrl_remove(struct platform_device *pdev);
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#endif
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