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If a property has an 'items' list, then a 'minItems' or 'maxItems' with the same size as the list is redundant and can be dropped. Note that is DT schema specific behavior and not standard json-schema behavior. The tooling will fixup the final schema adding any unspecified minItems/maxItems. This condition is partially checked with the meta-schema already, but only if both 'minItems' and 'maxItems' are equal to the 'items' length. An improved meta-schema is pending. Cc: Jens Axboe <axboe@kernel.dk> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Kamal Dasu <kdasu.kdev@gmail.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Vivien Didelot <vivien.didelot@gmail.com> Cc: Vladimir Oltean <olteanv@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de> Cc: Lee Jones <lee.jones@linaro.org> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Zhang Rui <rui.zhang@intel.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Wim Van Sebroeck <wim@linux-watchdog.org> Cc: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # for MMC Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-By: Vinod Koul <vkoul@kernel.org> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20210615191543.1043414-1-robh@kernel.org
111 lines
3.2 KiB
YAML
111 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas VMSA-Compatible IOMMU
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maintainers:
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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description:
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The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
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It provides address translation for bus masters outside of the CPU, each
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connected to the IPMMU through a port called micro-TLB.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,ipmmu-r8a73a4 # R-Mobile APE6
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- renesas,ipmmu-r8a7742 # RZ/G1H
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- renesas,ipmmu-r8a7743 # RZ/G1M
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- renesas,ipmmu-r8a7744 # RZ/G1N
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- renesas,ipmmu-r8a7745 # RZ/G1E
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- renesas,ipmmu-r8a7790 # R-Car H2
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- renesas,ipmmu-r8a7791 # R-Car M2-W
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- renesas,ipmmu-r8a7793 # R-Car M2-N
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- renesas,ipmmu-r8a7794 # R-Car E2
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- const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1
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- items:
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- enum:
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- renesas,ipmmu-r8a774a1 # RZ/G2M
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- renesas,ipmmu-r8a774b1 # RZ/G2N
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- renesas,ipmmu-r8a774c0 # RZ/G2E
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- renesas,ipmmu-r8a774e1 # RZ/G2H
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- renesas,ipmmu-r8a7795 # R-Car H3
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- renesas,ipmmu-r8a7796 # R-Car M3-W
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- renesas,ipmmu-r8a77961 # R-Car M3-W+
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- renesas,ipmmu-r8a77965 # R-Car M3-N
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- renesas,ipmmu-r8a77970 # R-Car V3M
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- renesas,ipmmu-r8a77980 # R-Car V3H
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- renesas,ipmmu-r8a77990 # R-Car E3
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- renesas,ipmmu-r8a77995 # R-Car D3
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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description:
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Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
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items:
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- description: non-secure mode
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- description: secure mode if supported
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'#iommu-cells':
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const: 1
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description:
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The number of the micro-TLB that the device is connected to.
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power-domains:
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maxItems: 1
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renesas,ipmmu-main:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Reference to the main IPMMU phandle plus 1 cell. The cell is
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the interrupt bit number associated with the particular cache IPMMU
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device. The interrupt bit number needs to match the main IPMMU IMSSTR
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register. Only used by cache IPMMU instances.
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required:
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- compatible
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- reg
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- '#iommu-cells'
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oneOf:
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- required:
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- interrupts
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- required:
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- renesas,ipmmu-main
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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not:
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contains:
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const: renesas,ipmmu-vmsa
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then:
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required:
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- power-domains
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examples:
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- |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7791-sysc.h>
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ipmmu_mx: iommu@fe951000 {
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compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
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reg = <0xfe951000 0x1000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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