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The ARM SMMU instantiations found on Tegra186 and later need inter- operation with the memory controller in order to correctly program stream ID overrides. Furthermore, on Tegra194 multiple instances of the SMMU can gang up to achieve higher throughput. In order to do this, they have to be programmed identically so that the memory controller can interleave memory accesses between them. Add the Tegra186 compatible string to make sure the interoperation with the memory controller can be enabled on that SoC generation. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210603164632.1000458-3-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
277 lines
8.4 KiB
YAML
277 lines
8.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM System MMU Architecture Implementation
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maintainers:
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- Will Deacon <will@kernel.org>
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- Robin Murphy <Robin.Murphy@arm.com>
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description: |+
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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properties:
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$nodename:
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pattern: "^iommu@[0-9a-f]*"
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compatible:
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oneOf:
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- description: Qcom SoCs implementing "arm,smmu-v2"
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items:
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- enum:
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- qcom,msm8996-smmu-v2
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- qcom,msm8998-smmu-v2
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- const: qcom,smmu-v2
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- description: Qcom SoCs implementing "arm,mmu-500"
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items:
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- enum:
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- qcom,sc7180-smmu-500
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- qcom,sc7280-smmu-500
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- qcom,sc8180x-smmu-500
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- qcom,sdm845-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "arm,smmu-v2"
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items:
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- enum:
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- qcom,sc7180-smmu-v2
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- qcom,sdm845-smmu-v2
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- const: qcom,adreno-smmu
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- const: qcom,smmu-v2
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- description: Marvell SoCs implementing "arm,mmu-500"
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items:
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- const: marvell,ap806-smmu-500
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- const: arm,mmu-500
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- description: NVIDIA SoCs that program two ARM MMU-500s identically
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items:
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- description: NVIDIA SoCs that require memory controller interaction
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and may program multiple ARM MMU-500s identically with the memory
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controller interleaving translations between multiple instances
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for improved performance.
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items:
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- enum:
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- const: nvidia,tegra194-smmu
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- const: nvidia,tegra186-smmu
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- const: nvidia,smmu-500
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- items:
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- const: arm,mmu-500
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- const: arm,smmu-v2
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- items:
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- enum:
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- arm,mmu-400
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- arm,mmu-401
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- const: arm,smmu-v1
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- enum:
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- arm,smmu-v1
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- arm,smmu-v2
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- arm,mmu-400
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- arm,mmu-401
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- arm,mmu-500
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- cavium,smmu-v2
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reg:
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minItems: 1
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maxItems: 2
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'#global-interrupts':
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description: The number of global interrupts exposed by the device.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
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'#iommu-cells':
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enum: [ 1, 2 ]
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description: |
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See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
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value of 1, each IOMMU specifier represents a distinct stream ID emitted
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by that device into the relevant SMMU.
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SMMUs with stream matching support and complex masters may use a value of
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2, where the second cell of the IOMMU specifier represents an SMR mask to
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combine with the ID in the first cell. Care must be taken to ensure the
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set of matched IDs does not result in conflicts.
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interrupts:
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minItems: 1
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maxItems: 388 # 260 plus 128 contexts
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description: |
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Interrupt list, with the first #global-interrupts entries corresponding to
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the global interrupts and any following entries corresponding to context
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interrupts, specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one interrupt per
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context bank. In the case of a single, combined interrupt, it must be
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listed multiple times.
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dma-coherent:
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description: |
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Present if page table walks made by the SMMU are cache coherent with the
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CPU.
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NOTE: this only applies to the SMMU itself, not masters connected
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upstream of the SMMU.
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calxeda,smmu-secure-config-access:
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type: boolean
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description:
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Enable proper handling of buggy implementations that always use secure
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access to SMMU configuration registers. In this case non-secure aliases of
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secure registers have to be used during SMMU configuration.
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stream-match-mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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For SMMUs supporting stream matching and using #iommu-cells = <1>,
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specifies a mask of bits to ignore when matching stream IDs (e.g. this may
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be programmed into the SMRn.MASK field of every stream match register
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used). For cases where it is desirable to ignore some portion of every
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Stream ID (e.g. for certain MMU-500 configurations given globally unique
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input IDs). This property is not valid for SMMUs using stream indexing, or
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using stream matching with #iommu-cells = <2>, and may be ignored if
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present in such cases.
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clock-names:
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items:
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- const: bus
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- const: iface
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clocks:
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items:
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- description: bus clock required for downstream bus access and for the
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smmu ptw
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- '#global-interrupts'
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- '#iommu-cells'
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- interrupts
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-smmu
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- nvidia,tegra186-smmu
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then:
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properties:
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reg:
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minItems: 1
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maxItems: 2
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else:
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properties:
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reg:
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maxItems: 1
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examples:
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- |+
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/* SMMU with stream matching or stream indexing */
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smmu1: iommu@ba5e0000 {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>, /* This is the first context interrupt */
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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#iommu-cells = <1>;
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};
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/* device with two stream IDs, 0 and 7 */
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master1 {
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iommus = <&smmu1 0>,
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<&smmu1 7>;
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};
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/* SMMU with stream matching */
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smmu2: iommu@ba5f0000 {
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compatible = "arm,smmu-v1";
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reg = <0xba5f0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 38 4>,
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<0 39 4>,
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<0 40 4>, /* This is the first context interrupt */
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<0 41 4>,
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<0 42 4>,
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<0 43 4>;
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#iommu-cells = <2>;
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};
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/* device with stream IDs 0 and 7 */
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master2 {
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iommus = <&smmu2 0 0>,
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<&smmu2 7 0>;
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};
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/* device with stream IDs 1, 17, 33 and 49 */
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master3 {
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iommus = <&smmu2 1 0x30>;
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};
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/* ARM MMU-500 with 10-bit stream ID input configuration */
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smmu3: iommu@ba600000 {
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compatible = "arm,mmu-500", "arm,smmu-v2";
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reg = <0xba600000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 44 4>,
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<0 45 4>,
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<0 46 4>, /* This is the first context interrupt */
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<0 47 4>,
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<0 48 4>,
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<0 49 4>;
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#iommu-cells = <1>;
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/* always ignore appended 5-bit TBU number */
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stream-match-mask = <0x7c00>;
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};
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bus {
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/* bus whose child devices emit one unique 10-bit stream
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ID each, but may master through multiple SMMU TBUs */
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iommu-map = <0 &smmu3 0 0x400>;
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};
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- |+
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/* Qcom's arm,smmu-v2 implementation */
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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smmu4: iommu@d00000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xd00000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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power-domains = <&mmcc 0>;
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clocks = <&mmcc 123>,
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<&mmcc 124>;
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clock-names = "bus", "iface";
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};
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