Finley Xiao 98dcc6be38 clk: rockchip: rk3128: Fix aclk_peri_src's parent ... According to the TRM there are no specific gpll_peri, cpll_peri, gpll_div2_peri or gpll_div3_peri gates, but a single clk_peri_src gate. Instead mux_clk_peri_src directly connects to the plls respectively the pll divider clocks. Fix this by creating a single gated composite. Also rename all occurrences of aclk_peri_src to clk_peri_src, since it is the parent for peri aclks, pclks and hclks. That name also matches the one used in the TRM. Fixes: f6022e88fa ("clk: rockchip: add clock controller for rk3128") Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [renamed aclk_peri_src -> clk_peri_src and added commit message] Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231127181415.11735-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2023-11-28 10:30:58 +01:00
..
clk-cpu.c	clk: rockchip: allow additional mux options for cpu-clock frequency changes	2022-11-14 15:34:18 +01:00
clk-ddr.c	clk: rockchip: Export rockchip_clk_register_ddrclk()	2020-09-22 15:16:37 +02:00
clk-half-divider.c	clk: rockchip: Demote non-conformant kernel-doc header in half-divider	2021-01-26 00:24:05 +01:00
clk-inverter.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
clk-mmc-phase.c	clk: rockchip: fix mmc get phase	2020-03-06 12:06:01 -08:00
clk-muxgrf.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
clk-pll.c	clk: rockchip: Fix memory leak in rockchip_clk_register_pll()	2022-11-23 14:51:30 +01:00
clk-px30.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3036.c	clk: rockchip: Add support for hclk_sfc on rk3036	2021-07-16 00:33:42 +02:00
clk-rk3128.c	clk: rockchip: rk3128: Fix aclk_peri_src's parent	2023-11-28 10:30:58 +01:00
clk-rk3188.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3228.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3288.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3308.c	clk: rockchip: make rk3308 ddrphy4x clock critical	2021-07-29 12:43:11 +02:00
clk-rk3328.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3368.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3399.c	clk: Use device_get_match_data()	2023-10-23 20:16:21 -07:00
clk-rk3568.c	clk: rockchip: rk3568: Add PLL rate for 292.5MHz	2023-11-16 21:26:06 +01:00
clk-rk3588.c	clk: rockchip: rk3588: make gate linked clocks critical	2023-04-18 00:54:04 +02:00
clk-rv1108.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rv1126.c	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next	2023-08-30 14:38:19 -07:00
clk.c	clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider	2023-04-05 12:09:27 -07:00
clk.h	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
Kconfig	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
Makefile	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
rst-rk3588.c	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
softrst.c	clk: rockchip: add lookup table support	2022-11-14 15:35:07 +01:00