linux/drivers/cxl
Dan Williams 98d2d3a264 cxl/core: Generalize dport enumeration in the core
The core houses infrastructure for decoder resources. A CXL port's
dports are more closely related to decoder infrastructure than topology
enumeration. Implement generic PCI based dport enumeration in the core,
i.e. arrange for existing root port enumeration from cxl_acpi to share
code with switch port enumeration which just amounts to a small
difference in a pci_walk_bus() invocation once the appropriate 'struct
pci_bus' has been retrieved.

Set the convention that decoder objects are registered after all dports
are enumerated. This enables userspace to know when the CXL core is
finished establishing 'dportX' links underneath the 'portX' object.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164368114191.354031.5270501846455462665.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-02-08 22:57:30 -08:00
..
core cxl/core: Generalize dport enumeration in the core 2022-02-08 22:57:30 -08:00
acpi.c cxl/core: Generalize dport enumeration in the core 2022-02-08 22:57:30 -08:00
cxl.h cxl/core: Generalize dport enumeration in the core 2022-02-08 22:57:30 -08:00
cxlmem.h cxl/memdev: Remove unused cxlmd field 2021-11-15 11:02:59 -08:00
cxlpci.h cxl/core: Generalize dport enumeration in the core 2022-02-08 22:57:30 -08:00
Kconfig cxl: Rename CXL_MEM to CXL_PCI 2022-02-08 22:57:27 -08:00
Makefile cxl: Rename CXL_MEM to CXL_PCI 2022-02-08 22:57:27 -08:00
pci.c cxl/pci: Rename pci.h to cxlpci.h 2022-02-08 22:57:30 -08:00
pmem.c cxl: Prove CXL locking 2022-02-08 22:57:29 -08:00