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e44abfed6f
The read-only DBI registers can be written only when the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set. Add accessors to enable and disable write permission, and use them instead of accessing MISC_CONTROL_1_OFF directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
351 lines
9.6 KiB
C
351 lines
9.6 KiB
C
/*
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* Synopsys Designware PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _PCIE_DESIGNWARE_H
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#define _PCIE_DESIGNWARE_H
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU_MIN 9000
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#define LINK_WAIT_IATU_MAX 10000
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK (0x3f << 16)
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#define PORT_LINK_MODE_1_LANES (0x1 << 16)
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#define PORT_LINK_MODE_2_LANES (0x3 << 16)
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#define PORT_LINK_MODE_4_LANES (0x7 << 16)
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#define PORT_LINK_MODE_8_LANES (0xf << 16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
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#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
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#define PCIE_MSI_ADDR_LO 0x820
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#define PCIE_MSI_ADDR_HI 0x824
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#define PCIE_MSI_INTR0_ENABLE 0x828
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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#define PCIE_MISC_CONTROL_1_OFF 0x8BC
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#define PCIE_DBI_RO_WR_EN (0x1 << 0)
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/*
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* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0C
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#define PCIE_ATU_UNR_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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/* Register address builder */
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
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((0x3 << 20) | ((region) << 9))
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#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
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((0x3 << 20) | ((region) << 9) | (0x1 << 8))
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#define MSI_MESSAGE_CONTROL 0x52
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#define MSI_CAP_MMC_SHIFT 1
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#define MSI_CAP_MME_SHIFT 4
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#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
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#define MSI_MESSAGE_ADDR_L32 0x54
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#define MSI_MESSAGE_ADDR_U32 0x58
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/*
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* Maximum number of MSI IRQs can be 256 per controller. But keep
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* it 32 as of now. Probably we will never need more than 32. If needed,
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* then increment it in multiple of 32.
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*/
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#define MAX_MSI_IRQS 32
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#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
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struct pcie_port;
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struct dw_pcie;
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struct dw_pcie_ep;
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enum dw_pcie_region_type {
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DW_PCIE_REGION_UNKNOWN,
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DW_PCIE_REGION_INBOUND,
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DW_PCIE_REGION_OUTBOUND,
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};
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enum dw_pcie_device_mode {
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DW_PCIE_UNKNOWN_TYPE,
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DW_PCIE_EP_TYPE,
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DW_PCIE_LEG_EP_TYPE,
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DW_PCIE_RC_TYPE,
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};
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struct dw_pcie_host_ops {
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int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
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int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
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int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val);
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int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val);
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int (*host_init)(struct pcie_port *pp);
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void (*msi_set_irq)(struct pcie_port *pp, int irq);
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void (*msi_clear_irq)(struct pcie_port *pp, int irq);
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phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
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u32 (*get_msi_data)(struct pcie_port *pp, int pos);
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void (*scan_bus)(struct pcie_port *pp);
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int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
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};
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struct pcie_port {
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u8 root_bus_nr;
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u64 cfg0_base;
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void __iomem *va_cfg0_base;
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u32 cfg0_size;
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u64 cfg1_base;
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void __iomem *va_cfg1_base;
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u32 cfg1_size;
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resource_size_t io_base;
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phys_addr_t io_bus_addr;
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u32 io_size;
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u64 mem_base;
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phys_addr_t mem_bus_addr;
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u32 mem_size;
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struct resource *cfg;
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struct resource *io;
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struct resource *mem;
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struct resource *busn;
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int irq;
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const struct dw_pcie_host_ops *ops;
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int msi_irq;
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struct irq_domain *irq_domain;
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unsigned long msi_data;
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DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
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};
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enum dw_pcie_as_type {
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DW_PCIE_AS_UNKNOWN,
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DW_PCIE_AS_MEM,
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DW_PCIE_AS_IO,
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};
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struct dw_pcie_ep_ops {
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void (*ep_init)(struct dw_pcie_ep *ep);
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int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
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u8 interrupt_num);
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};
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struct dw_pcie_ep {
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struct pci_epc *epc;
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struct dw_pcie_ep_ops *ops;
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phys_addr_t phys_base;
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size_t addr_size;
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u8 bar_to_atu[6];
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phys_addr_t *outbound_addr;
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unsigned long ib_window_map;
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unsigned long ob_window_map;
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u32 num_ib_windows;
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u32 num_ob_windows;
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};
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struct dw_pcie_ops {
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u64 (*cpu_addr_fixup)(u64 cpu_addr);
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u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size);
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void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size, u32 val);
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int (*link_up)(struct dw_pcie *pcie);
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int (*start_link)(struct dw_pcie *pcie);
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void (*stop_link)(struct dw_pcie *pcie);
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};
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struct dw_pcie {
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struct device *dev;
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void __iomem *dbi_base;
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void __iomem *dbi_base2;
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u32 num_viewport;
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u8 iatu_unroll_enabled;
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struct pcie_port pp;
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struct dw_pcie_ep ep;
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const struct dw_pcie_ops *ops;
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};
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#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
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#define to_dw_pcie_from_ep(endpoint) \
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container_of((endpoint), struct dw_pcie, ep)
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int dw_pcie_read(void __iomem *addr, int size, u32 *val);
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int dw_pcie_write(void __iomem *addr, int size, u32 val);
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u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size);
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void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size, u32 val);
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int dw_pcie_link_up(struct dw_pcie *pci);
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int dw_pcie_wait_for_link(struct dw_pcie *pci);
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void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
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int type, u64 cpu_addr, u64 pci_addr,
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u32 size);
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int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
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u64 cpu_addr, enum dw_pcie_as_type as_type);
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void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
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enum dw_pcie_region_type type);
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void dw_pcie_setup(struct dw_pcie *pci);
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static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
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}
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static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
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}
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static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
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}
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static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
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}
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static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
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}
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static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
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}
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static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val);
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}
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static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
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}
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static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
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{
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u32 reg;
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u32 val;
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reg = PCIE_MISC_CONTROL_1_OFF;
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val = dw_pcie_readl_dbi(pci, reg);
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val |= PCIE_DBI_RO_WR_EN;
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dw_pcie_writel_dbi(pci, reg, val);
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}
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static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
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{
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u32 reg;
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u32 val;
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reg = PCIE_MISC_CONTROL_1_OFF;
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val = dw_pcie_readl_dbi(pci, reg);
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val &= ~PCIE_DBI_RO_WR_EN;
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dw_pcie_writel_dbi(pci, reg, val);
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}
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#ifdef CONFIG_PCIE_DW_HOST
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
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void dw_pcie_msi_init(struct pcie_port *pp);
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void dw_pcie_setup_rc(struct pcie_port *pp);
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int dw_pcie_host_init(struct pcie_port *pp);
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#else
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static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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return IRQ_NONE;
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}
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static inline void dw_pcie_msi_init(struct pcie_port *pp)
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{
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}
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static inline void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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}
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static inline int dw_pcie_host_init(struct pcie_port *pp)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_PCIE_DW_EP
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void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
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int dw_pcie_ep_init(struct dw_pcie_ep *ep);
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void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
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#else
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static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
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{
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}
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static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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return 0;
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}
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static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
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{
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}
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#endif
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#endif /* _PCIE_DESIGNWARE_H */
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