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7e5ac1f220
One of a class of bugs pointed out by Lars in a recent review.
iio_push_to_buffers_with_timestamp assumes the buffer used is aligned
to the size of the timestamp (8 bytes). This is not guaranteed in
this driver which uses a 16 byte u8 array on the stack As Lars also noted
this anti pattern can involve a leak of data to userspace and that
indeed can happen here. We close both issues by moving to
a suitable structure in the iio_priv() data with alignment
ensured by use of an explicit c structure. This data is allocated
with kzalloc so no data can leak appart from previous readings.
The force alignment of ts is not strictly necessary in this particularly
case but does make the code less fragile.
Fixes: a84ef0d181 ("iio: accel: add Freescale MMA7455L/MMA7456L 3-axis accelerometer driver")
Reported-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: <Stable@vger.kernel.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
315 lines
7.2 KiB
C
315 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IIO accel core driver for Freescale MMA7455L 3-axis 10-bit accelerometer
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* Copyright 2015 Joachim Eastwood <manabian@gmail.com>
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*
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* UNSUPPORTED hardware features:
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* - 8-bit mode with different scales
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* - INT1/INT2 interrupts
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* - Offset calibration
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* - Events
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*/
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include "mma7455.h"
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#define MMA7455_REG_XOUTL 0x00
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#define MMA7455_REG_XOUTH 0x01
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#define MMA7455_REG_YOUTL 0x02
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#define MMA7455_REG_YOUTH 0x03
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#define MMA7455_REG_ZOUTL 0x04
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#define MMA7455_REG_ZOUTH 0x05
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#define MMA7455_REG_STATUS 0x09
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#define MMA7455_STATUS_DRDY BIT(0)
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#define MMA7455_REG_WHOAMI 0x0f
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#define MMA7455_WHOAMI_ID 0x55
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#define MMA7455_REG_MCTL 0x16
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#define MMA7455_MCTL_MODE_STANDBY 0x00
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#define MMA7455_MCTL_MODE_MEASURE 0x01
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#define MMA7455_REG_CTL1 0x18
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#define MMA7455_CTL1_DFBW_MASK BIT(7)
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#define MMA7455_CTL1_DFBW_125HZ BIT(7)
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#define MMA7455_CTL1_DFBW_62_5HZ 0
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#define MMA7455_REG_TW 0x1e
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/*
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* When MMA7455 is used in 10-bit it has a fullscale of -8g
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* corresponding to raw value -512. The userspace interface
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* uses m/s^2 and we declare micro units.
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* So scale factor is given by:
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* g * 8 * 1e6 / 512 = 153228.90625, with g = 9.80665
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*/
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#define MMA7455_10BIT_SCALE 153229
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struct mma7455_data {
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struct regmap *regmap;
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/*
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* Used to reorganize data. Will ensure correct alignment of
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* the timestamp if present
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*/
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struct {
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__le16 channels[3];
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s64 ts __aligned(8);
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} scan;
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};
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static int mma7455_drdy(struct mma7455_data *mma7455)
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{
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struct device *dev = regmap_get_device(mma7455->regmap);
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unsigned int reg;
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int tries = 3;
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int ret;
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while (tries-- > 0) {
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ret = regmap_read(mma7455->regmap, MMA7455_REG_STATUS, ®);
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if (ret)
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return ret;
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if (reg & MMA7455_STATUS_DRDY)
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return 0;
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msleep(20);
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}
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dev_warn(dev, "data not ready\n");
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return -EIO;
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}
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static irqreturn_t mma7455_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct mma7455_data *mma7455 = iio_priv(indio_dev);
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int ret;
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ret = mma7455_drdy(mma7455);
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if (ret)
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goto done;
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ret = regmap_bulk_read(mma7455->regmap, MMA7455_REG_XOUTL,
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mma7455->scan.channels,
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sizeof(mma7455->scan.channels));
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if (ret)
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goto done;
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iio_push_to_buffers_with_timestamp(indio_dev, &mma7455->scan,
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iio_get_time_ns(indio_dev));
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done:
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static int mma7455_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct mma7455_data *mma7455 = iio_priv(indio_dev);
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unsigned int reg;
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__le16 data;
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (iio_buffer_enabled(indio_dev))
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return -EBUSY;
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ret = mma7455_drdy(mma7455);
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if (ret)
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return ret;
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ret = regmap_bulk_read(mma7455->regmap, chan->address, &data,
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sizeof(data));
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if (ret)
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return ret;
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*val = sign_extend32(le16_to_cpu(data), 9);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = 0;
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*val2 = MMA7455_10BIT_SCALE;
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return IIO_VAL_INT_PLUS_MICRO;
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case IIO_CHAN_INFO_SAMP_FREQ:
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ret = regmap_read(mma7455->regmap, MMA7455_REG_CTL1, ®);
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if (ret)
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return ret;
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if (reg & MMA7455_CTL1_DFBW_MASK)
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*val = 250;
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else
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*val = 125;
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return IIO_VAL_INT;
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}
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return -EINVAL;
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}
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static int mma7455_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct mma7455_data *mma7455 = iio_priv(indio_dev);
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int i;
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switch (mask) {
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case IIO_CHAN_INFO_SAMP_FREQ:
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if (val == 250 && val2 == 0)
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i = MMA7455_CTL1_DFBW_125HZ;
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else if (val == 125 && val2 == 0)
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i = MMA7455_CTL1_DFBW_62_5HZ;
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else
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return -EINVAL;
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return regmap_update_bits(mma7455->regmap, MMA7455_REG_CTL1,
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MMA7455_CTL1_DFBW_MASK, i);
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case IIO_CHAN_INFO_SCALE:
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/* In 10-bit mode there is only one scale available */
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if (val == 0 && val2 == MMA7455_10BIT_SCALE)
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return 0;
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break;
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}
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return -EINVAL;
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}
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static IIO_CONST_ATTR(sampling_frequency_available, "125 250");
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static struct attribute *mma7455_attributes[] = {
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&iio_const_attr_sampling_frequency_available.dev_attr.attr,
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NULL
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};
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static const struct attribute_group mma7455_group = {
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.attrs = mma7455_attributes,
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};
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static const struct iio_info mma7455_info = {
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.attrs = &mma7455_group,
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.read_raw = mma7455_read_raw,
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.write_raw = mma7455_write_raw,
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};
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#define MMA7455_CHANNEL(axis, idx) { \
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.type = IIO_ACCEL, \
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.modified = 1, \
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.address = MMA7455_REG_##axis##OUTL,\
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.channel2 = IIO_MOD_##axis, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = idx, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 10, \
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.storagebits = 16, \
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.endianness = IIO_LE, \
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}, \
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}
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static const struct iio_chan_spec mma7455_channels[] = {
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MMA7455_CHANNEL(X, 0),
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MMA7455_CHANNEL(Y, 1),
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MMA7455_CHANNEL(Z, 2),
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IIO_CHAN_SOFT_TIMESTAMP(3),
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};
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static const unsigned long mma7455_scan_masks[] = {0x7, 0};
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const struct regmap_config mma7455_core_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = MMA7455_REG_TW,
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};
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EXPORT_SYMBOL_GPL(mma7455_core_regmap);
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int mma7455_core_probe(struct device *dev, struct regmap *regmap,
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const char *name)
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{
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struct mma7455_data *mma7455;
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struct iio_dev *indio_dev;
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unsigned int reg;
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int ret;
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ret = regmap_read(regmap, MMA7455_REG_WHOAMI, ®);
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if (ret) {
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dev_err(dev, "unable to read reg\n");
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return ret;
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}
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if (reg != MMA7455_WHOAMI_ID) {
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dev_err(dev, "device id mismatch\n");
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return -ENODEV;
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}
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indio_dev = devm_iio_device_alloc(dev, sizeof(*mma7455));
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if (!indio_dev)
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return -ENOMEM;
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dev_set_drvdata(dev, indio_dev);
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mma7455 = iio_priv(indio_dev);
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mma7455->regmap = regmap;
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indio_dev->info = &mma7455_info;
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indio_dev->name = name;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = mma7455_channels;
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indio_dev->num_channels = ARRAY_SIZE(mma7455_channels);
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indio_dev->available_scan_masks = mma7455_scan_masks;
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regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
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MMA7455_MCTL_MODE_MEASURE);
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ret = iio_triggered_buffer_setup(indio_dev, NULL,
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mma7455_trigger_handler, NULL);
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if (ret) {
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dev_err(dev, "unable to setup triggered buffer\n");
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return ret;
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}
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ret = iio_device_register(indio_dev);
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if (ret) {
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dev_err(dev, "unable to register device\n");
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iio_triggered_buffer_cleanup(indio_dev);
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(mma7455_core_probe);
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int mma7455_core_remove(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct mma7455_data *mma7455 = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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iio_triggered_buffer_cleanup(indio_dev);
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regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
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MMA7455_MCTL_MODE_STANDBY);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mma7455_core_remove);
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MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
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MODULE_DESCRIPTION("Freescale MMA7455L core accelerometer driver");
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MODULE_LICENSE("GPL v2");
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