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35f4e9d753
amda ss is consisted of dma and audio ss in qxp which are also used in qm. Let's split them into two ss for better code reuse. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
273 lines
6.0 KiB
Plaintext
273 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017~2018 NXP
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*/
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/dts-v1/;
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#include "imx8qxp.dtsi"
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/ {
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model = "Freescale i.MX8QXP MEK";
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compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
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chosen {
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stdout-path = &lpuart0;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x40000000>;
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};
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reg_usdhc2_vmmc: usdhc2-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "SD1_SPWR";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&dsp {
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
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status = "okay";
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i2c-switch@71 {
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compatible = "nxp,pca9646", "nxp,pca9546";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x71>;
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reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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max7322: gpio@68 {
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compatible = "maxim,max7322";
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reg = <0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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pressure-sensor@60 {
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compatible = "fsl,mpl3115";
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reg = <0x60>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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pca9557_a: gpio@1a {
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compatible = "nxp,pca9557";
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reg = <0x1a>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_b: gpio@1d {
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compatible = "nxp,pca9557";
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reg = <0x1d>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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light-sensor@44 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_isl29023>;
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compatible = "isil,isl29023";
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reg = <0x44>;
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interrupt-parent = <&lsio_gpio1>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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};
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&scu_key {
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status = "okay";
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};
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&thermal_zones {
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pmic-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
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trips {
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pmic_alert0: trip0 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "passive";
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};
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pmic_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&pmic_alert0>;
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cooling-device =
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<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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&usdhc1 {
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assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
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IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
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IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
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IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
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IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
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IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
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IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
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IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
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IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
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IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
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IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
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IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
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>;
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};
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pinctrl_ioexp_rst: ioexprstgrp {
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fsl,pins = <
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IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
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>;
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};
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pinctrl_isl29023: isl29023grp {
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fsl,pins = <
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IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
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IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
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IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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