mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-02 08:34:20 +08:00
c44094eee3
arch_dma_prep_coherent() is called when preparing a non-cacheable region for a consistent DMA buffer allocation. Since the buffer pages may previously have been written via a cacheable mapping and consequently allocated as dirty cachelines, the purpose of this function is to remove these dirty lines from the cache, writing them back so that the non-coherent device is able to see them. On arm64, this operation can be achieved with a clean to the point of coherency; a subsequent invalidation is not required and serves little purpose in the presence of a cacheable alias (e.g. the linear map), since clean lines can be speculatively fetched back into the cache after the invalidation operation has completed. Relax the cache maintenance in arch_dma_prep_coherent() so that only a clean, and not a clean-and-invalidate operation is performed. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220823122111.17439-1-will@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Copyright (C) 2012 ARM Ltd.
|
|
* Author: Catalin Marinas <catalin.marinas@arm.com>
|
|
*/
|
|
|
|
#include <linux/gfp.h>
|
|
#include <linux/cache.h>
|
|
#include <linux/dma-map-ops.h>
|
|
#include <linux/dma-iommu.h>
|
|
#include <xen/xen.h>
|
|
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/xen/xen-ops.h>
|
|
|
|
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
|
|
enum dma_data_direction dir)
|
|
{
|
|
unsigned long start = (unsigned long)phys_to_virt(paddr);
|
|
|
|
dcache_clean_poc(start, start + size);
|
|
}
|
|
|
|
void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
|
|
enum dma_data_direction dir)
|
|
{
|
|
unsigned long start = (unsigned long)phys_to_virt(paddr);
|
|
|
|
if (dir == DMA_TO_DEVICE)
|
|
return;
|
|
|
|
dcache_inval_poc(start, start + size);
|
|
}
|
|
|
|
void arch_dma_prep_coherent(struct page *page, size_t size)
|
|
{
|
|
unsigned long start = (unsigned long)page_address(page);
|
|
|
|
dcache_clean_poc(start, start + size);
|
|
}
|
|
|
|
#ifdef CONFIG_IOMMU_DMA
|
|
void arch_teardown_dma_ops(struct device *dev)
|
|
{
|
|
dev->dma_ops = NULL;
|
|
}
|
|
#endif
|
|
|
|
void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
|
const struct iommu_ops *iommu, bool coherent)
|
|
{
|
|
int cls = cache_line_size_of_cpu();
|
|
|
|
WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
|
|
TAINT_CPU_OUT_OF_SPEC,
|
|
"%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
|
|
dev_driver_string(dev), dev_name(dev),
|
|
ARCH_DMA_MINALIGN, cls);
|
|
|
|
dev->dma_coherent = coherent;
|
|
if (iommu)
|
|
iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
|
|
|
|
xen_setup_dma_ops(dev);
|
|
}
|