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The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
/*
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* Copyright (C) 2002 ARM Ltd.
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* Copyright (C) 2008 STMicroelctronics.
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* Copyright (C) 2009 ST-Ericsson.
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* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
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*
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* This file is based on arm realview platform
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "setup.h"
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#include "db8500-regs.h"
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#include "id.h"
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/* This is called from headsmp.S to wakeup the secondary core */
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extern void u8500_secondary_startup(void);
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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static void __iomem *scu_base_addr(void)
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{
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if (cpu_is_u8500_family() || cpu_is_ux540_family())
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return __io_address(U8500_SCU_BASE);
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else
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ux500_unknown_soc();
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return NULL;
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void ux500_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*/
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write_pen_release(cpu_logical_map(cpu));
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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if (pen_release == -1)
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break;
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init wakeup_secondary(void)
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{
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void __iomem *backupram;
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if (cpu_is_u8500_family() || cpu_is_ux540_family())
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backupram = __io_address(U8500_BACKUPRAM0_BASE);
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else
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ux500_unknown_soc();
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/*
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* write the address of secondary startup into the backup ram register
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* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
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* backup ram register at offset 0x1FF0, which is what boot rom code
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* is waiting for. This would wake up the secondary core from WFE
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*/
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#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
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__raw_writel(virt_to_phys(u8500_secondary_startup),
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backupram + UX500_CPU1_JUMPADDR_OFFSET);
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#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
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__raw_writel(0xA1FEED01,
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backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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mb();
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init ux500_smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base_addr());
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wakeup_secondary();
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}
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struct smp_operations ux500_smp_ops __initdata = {
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.smp_init_cpus = ux500_smp_init_cpus,
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.smp_prepare_cpus = ux500_smp_prepare_cpus,
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.smp_secondary_init = ux500_secondary_init,
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.smp_boot_secondary = ux500_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = ux500_cpu_die,
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#endif
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};
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