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96c3c9e78f
linux/arch/powerpc/perf
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Catalin Udma 96c3c9e78f powerpc/perf: increase the perf HW events to 6 
This change is required after the e6500 perf support has been added.
There are 6 counters in e6500 core instead of 4 in e500 core and
the MAX_HWEVENTS counter should be changed accordingly from 4 to 6.
Added also runtime check for counters overflow.

Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-07 18:38:03 -05:00
..
bhrb.S powerpc/perf: Add basic assembly code to read BHRB entries on POWER8 2013-04-26 16:11:11 +10:00
callchain.c powerpc/perf: Use perf_instruction_pointer in callchains 2012-07-10 19:18:46 +10:00
core-book3s.c powerpc/perf: Core EBB support for 64-bit book3s 2013-07-01 11:50:10 +10:00
core-fsl-emb.c powerpc/perf: increase the perf HW events to 6 2013-08-07 18:38:03 -05:00
e500-pmu.c powerpc/perf: Add stalled-cycles events 2013-01-10 17:00:56 +11:00
Makefile powerpc/perf: Add basic assembly code to read BHRB entries on POWER8 2013-04-26 16:11:11 +10:00
mpc7450-pmu.c
power4-pmu.c powerpc/perf: Fix instruction address sampling on 970 and Power4 2012-03-28 11:33:24 +11:00
power5-pmu.c powerpc/perf: Add an explict flag indicating presence of SLOT field 2013-04-26 16:11:07 +10:00
power5+-pmu.c powerpc/perf: Add an explict flag indicating presence of SLOT field 2013-04-26 16:11:07 +10:00
power6-pmu.c
power7-pmu.c perf tools: fix a typo of a Power7 event name 2013-07-08 17:40:05 -03:00
power8-pmu.c powerpc/perf: Add power8 EBB support 2013-07-01 11:50:13 +10:00
ppc970-pmu.c powerpc/perf: Fix instruction address sampling on 970 and Power4 2012-03-28 11:33:24 +11:00