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6bd33e1ece
The kernel runs in M-mode without using page tables, and thus can't run bare metal without help from additional firmware. Most of the patch is just stubbing out code not needed without page tables, but there is an interesting detail in the signals implementation: - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO entry point, but the ELF VDSO is not supported for nommu Linux. We instead copy the code to call the syscall onto the stack. In addition to enabling the nommu code a new defconfig for a small kernel image that can run in nommu mode on qemu is also provided, to run a kernel in qemu you can use the following command line: qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \ -kernel arch/riscv/boot/loader \ -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards around PCI_IOBASE definition to fix build issues; fixed checkpatch issues; move the PCI_IO_* and VMEMMAP address space macros along with the others; resolve sparse warning] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 SiFive
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*/
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#ifdef CONFIG_SMP
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#include <asm/sbi.h>
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static void ipi_remote_fence_i(void *info)
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{
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return local_flush_icache_all();
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}
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void flush_icache_all(void)
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{
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_remote_fence_i(NULL);
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else
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on_each_cpu(ipi_remote_fence_i, NULL, 1);
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}
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm == current->active_mm && local) {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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} else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
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cpumask_t hartid_mask;
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riscv_cpuid_to_hartid_mask(&others, &hartid_mask);
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sbi_remote_fence_i(cpumask_bits(&hartid_mask));
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} else {
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on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
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}
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preempt_enable();
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_MMU
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void flush_icache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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flush_icache_all();
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}
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#endif /* CONFIG_MMU */
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