谢致邦 (XIE Zhibang) 968dc5a0ea MIPS: Loongson: Set Loongson32 to MIPS32R1 ... LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit)) is the CPU core (microarchitecture) of Loongson 1A/1B/1C. According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2 instruction set. In the manual, LS232 implements all of the MIPS32R2 instruction set except the FPU instructions, and LS232 also implements 5 FPU instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt, FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt. But a bug of the DI instruction has been found during tests, the DI instruction can not disable interrupts in arch_local_irq_disable() with CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases. [paul.burton@mips.com: - Remove the _MIPS_ISA redefinition to match the change made for the generic MIPSr1 CPUs by commit 344ebf0994 ("MIPS: Always use -march=<arch>, not -<arch> shortcuts").] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16155/ Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org		2018-07-30 18:54:15 -07:00
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common	MIPS: loongson1: set default number of rx and tx queues for stmmac	2017-10-09 14:53:38 +02:00
ls1b	MIPS: Loongson1: Add watchdog support for Loongson1 board	2017-01-03 16:34:42 +01:00
ls1c	MIPS: Loongson1: Add watchdog support for Loongson1 board	2017-01-03 16:34:42 +01:00
Kconfig	MIPS: use generic dma noncoherent ops for simple noncoherent platforms	2018-06-24 09:26:05 -07:00
Makefile	MIPS: Loongson1C: Add board support	2016-10-04 16:13:57 +02:00
Platform	MIPS: Loongson: Set Loongson32 to MIPS32R1	2018-07-30 18:54:15 -07:00