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966414da2d
This will provide a better code flow that fits the logic Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
271 lines
7.8 KiB
C
271 lines
7.8 KiB
C
/*
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* Copyright (c) 2011 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/* ***** SDIO interface chip backplane handle functions ***** */
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#include <linux/types.h>
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#include <linux/netdevice.h>
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#include <linux/mmc/card.h>
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#include <chipcommon.h>
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#include <brcm_hw_ids.h>
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#include <brcmu_wifi.h>
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#include <brcmu_utils.h>
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#include <soc.h>
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#include "dhd.h"
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#include "dhd_dbg.h"
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#include "sdio_host.h"
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#include "sdio_chip.h"
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/* chip core base & ramsize */
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/* bcm4329 */
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/* SDIO device core, ID 0x829 */
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#define BCM4329_CORE_BUS_BASE 0x18011000
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/* internal memory core, ID 0x80e */
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#define BCM4329_CORE_SOCRAM_BASE 0x18003000
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/* ARM Cortex M3 core, ID 0x82a */
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#define BCM4329_CORE_ARM_BASE 0x18002000
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#define BCM4329_RAMSIZE 0x48000
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/* SB regs */
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/* sbidhigh */
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#define SBIDH_RC_MASK 0x000f /* revision code */
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#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
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#define SBIDH_RCE_SHIFT 8
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#define SBCOREREV(sbidh) \
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((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
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((sbidh) & SBIDH_RC_MASK))
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#define SBIDH_CC_MASK 0x8ff0 /* core code */
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#define SBIDH_CC_SHIFT 4
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#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
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#define SBIDH_VC_SHIFT 16
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void
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brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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{
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u32 regdata;
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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if (regdata & SBTML_RESET)
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return;
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
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/*
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* set target reject and spin until busy is clear
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* (preserve core-specific bits)
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*/
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
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4, regdata | SBTML_REJ);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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udelay(1);
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SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatehigh), 4) &
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SBTMH_BUSY), 100000);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatehigh), 4);
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if (regdata & SBTMH_BUSY)
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brcmf_dbg(ERROR, "core state still busy\n");
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbidlow), 4);
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if (regdata & SBIDL_INIT) {
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4) |
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SBIM_RJ;
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbimstate), 4,
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regdata);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4);
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udelay(1);
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SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4) &
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SBIM_BY), 100000);
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}
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/* set reset and reject while enabling the clocks */
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4,
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(((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
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SBTML_REJ | SBTML_RESET));
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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udelay(10);
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/* clear the initiator reject bit */
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbidlow), 4);
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if (regdata & SBIDL_INIT) {
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4) &
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~SBIM_RJ;
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbimstate), 4,
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regdata);
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}
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}
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/* leave reset and reject asserted */
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
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(SBTML_REJ | SBTML_RESET));
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udelay(1);
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}
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static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci, u32 regs)
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{
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u32 regdata;
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/*
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* Get CC core rev
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* Chipid is assume to be at offset 0 from regs arg
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* For different chiptypes or old sdio hosts w/o chipcommon,
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* other ways of recognition should be added here.
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*/
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ci->cccorebase = regs;
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, chipid), 4);
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ci->chip = regdata & CID_ID_MASK;
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ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
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brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
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/* Address of cores for new chips should be added here */
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switch (ci->chip) {
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case BCM4329_CHIP_ID:
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ci->buscorebase = BCM4329_CORE_BUS_BASE;
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ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
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ci->armcorebase = BCM4329_CORE_ARM_BASE;
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ci->ramsize = BCM4329_RAMSIZE;
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break;
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default:
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brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
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return -ENODEV;
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}
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return 0;
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}
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static int
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brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev)
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{
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int err = 0;
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u8 clkval, clkset;
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/* Try forcing SDIO core to do ALPAvail request only */
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clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
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brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
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if (err) {
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brcmf_dbg(ERROR, "error writing for HT off\n");
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return err;
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}
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/* If register supported, wait for ALPAvail and then force ALP */
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/* This may take up to 15 milliseconds */
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clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR, NULL);
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if ((clkval & ~SBSDIO_AVBITS) != clkset) {
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brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
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clkset, clkval);
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return -EACCES;
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}
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SPINWAIT(((clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
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!SBSDIO_ALPAV(clkval)),
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PMU_MAX_TRANSITION_DLY);
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if (!SBSDIO_ALPAV(clkval)) {
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brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
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clkval);
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return -EBUSY;
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}
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clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
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brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
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SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
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udelay(65);
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/* Also, disable the extra SDIO pull-ups */
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brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
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SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
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return 0;
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}
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static void
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brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci)
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{
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u32 regdata;
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/* get chipcommon rev */
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(ci->cccorebase, sbidhigh), 4);
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ci->ccrev = SBCOREREV(regdata);
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/* get chipcommon capabilites */
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ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, capabilities), 4);
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/* get pmu caps & rev */
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if (ci->cccaps & CC_CAP_PMU) {
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ci->pmucaps = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
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ci->pmurev = ci->pmucaps & PCAP_REV_MASK;
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}
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(ci->buscorebase, sbidhigh), 4);
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ci->buscorerev = SBCOREREV(regdata);
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ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
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brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
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ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
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/*
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* Make sure any on-chip ARM is off (in case strapping is wrong),
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* or downloaded code was already running.
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*/
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brcmf_sdio_chip_coredisable(sdiodev, ci->armcorebase);
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}
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int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci, u32 regs)
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{
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int ret = 0;
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ret = brcmf_sdio_chip_buscoreprep(sdiodev);
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if (ret != 0)
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return ret;
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ret = brcmf_sdio_chip_recognition(sdiodev, ci, regs);
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if (ret != 0)
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return ret;
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brcmf_sdio_chip_buscoresetup(sdiodev, ci);
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return ret;
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}
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