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d223f98f02
The compute shader dispatch interface is pretty simple -- just pass in
the regs that userspace has passed us, with no CLs to run. However,
with no CL to run it means that we need to do manual cache flushing of
the L2 after the HW execution completes (for SSBO, atomic, and
image_load_store writes that are the output of compute shaders).
This doesn't yet expose the L2 cache's ability to have a region of the
address space not write back to memory (which could be used for
shared_var storage).
So far, the Mesa side has been tested on V3D v4.2 simpenrose (passing
the ES31 tests), and on the kernel side on 7278 (failing atomic
compswap tests in a way that doesn't reproduce on simpenrose).
v2: Fix excessive allocation for the clean_job (reported by Dan
Carpenter). Keep refs on jobs until clean_job is finished, to
avoid spurious MMU errors if the output BOs are freed by userspace
before L2 cleaning is finished.
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190416225856.20264-4-eric@anholt.net
Acked-by: Rob Clark <robdclark@gmail.com>
260 lines
7.1 KiB
C
260 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2014-2018 Broadcom */
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#include <linux/circ_buf.h>
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include <linux/pm_runtime.h>
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#include <linux/seq_file.h>
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#include <drm/drmP.h>
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#define REGDEF(reg) { reg, #reg }
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struct v3d_reg_def {
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u32 reg;
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const char *name;
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};
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static const struct v3d_reg_def v3d_hub_reg_defs[] = {
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REGDEF(V3D_HUB_AXICFG),
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REGDEF(V3D_HUB_UIFCFG),
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REGDEF(V3D_HUB_IDENT0),
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REGDEF(V3D_HUB_IDENT1),
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REGDEF(V3D_HUB_IDENT2),
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REGDEF(V3D_HUB_IDENT3),
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REGDEF(V3D_HUB_INT_STS),
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REGDEF(V3D_HUB_INT_MSK_STS),
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};
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static const struct v3d_reg_def v3d_gca_reg_defs[] = {
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REGDEF(V3D_GCA_SAFE_SHUTDOWN),
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REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
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};
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static const struct v3d_reg_def v3d_core_reg_defs[] = {
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REGDEF(V3D_CTL_IDENT0),
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REGDEF(V3D_CTL_IDENT1),
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REGDEF(V3D_CTL_IDENT2),
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REGDEF(V3D_CTL_MISCCFG),
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REGDEF(V3D_CTL_INT_STS),
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REGDEF(V3D_CTL_INT_MSK_STS),
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REGDEF(V3D_CLE_CT0CS),
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REGDEF(V3D_CLE_CT0CA),
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REGDEF(V3D_CLE_CT0EA),
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REGDEF(V3D_CLE_CT1CS),
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REGDEF(V3D_CLE_CT1CA),
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REGDEF(V3D_CLE_CT1EA),
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REGDEF(V3D_PTB_BPCA),
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REGDEF(V3D_PTB_BPCS),
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REGDEF(V3D_MMU_CTL),
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REGDEF(V3D_MMU_VIO_ADDR),
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REGDEF(V3D_GMP_STATUS),
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REGDEF(V3D_GMP_CFG),
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REGDEF(V3D_GMP_VIO_ADDR),
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};
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static const struct v3d_reg_def v3d_csd_reg_defs[] = {
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REGDEF(V3D_CSD_STATUS),
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REGDEF(V3D_CSD_CURRENT_CFG0),
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REGDEF(V3D_CSD_CURRENT_CFG1),
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REGDEF(V3D_CSD_CURRENT_CFG2),
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REGDEF(V3D_CSD_CURRENT_CFG3),
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REGDEF(V3D_CSD_CURRENT_CFG4),
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REGDEF(V3D_CSD_CURRENT_CFG5),
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REGDEF(V3D_CSD_CURRENT_CFG6),
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};
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static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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int i, core;
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for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
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V3D_READ(v3d_hub_reg_defs[i].reg));
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}
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if (v3d->ver < 41) {
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for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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v3d_gca_reg_defs[i].name,
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v3d_gca_reg_defs[i].reg,
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V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
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}
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}
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for (core = 0; core < v3d->cores; core++) {
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for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
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seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
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core,
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v3d_core_reg_defs[i].name,
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v3d_core_reg_defs[i].reg,
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V3D_CORE_READ(core,
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v3d_core_reg_defs[i].reg));
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}
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if (v3d_has_csd(v3d)) {
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for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
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seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
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core,
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v3d_csd_reg_defs[i].name,
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v3d_csd_reg_defs[i].reg,
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V3D_CORE_READ(core,
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v3d_csd_reg_defs[i].reg));
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}
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}
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}
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return 0;
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}
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static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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u32 ident0, ident1, ident2, ident3, cores;
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int ret, core;
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ret = pm_runtime_get_sync(v3d->dev);
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if (ret < 0)
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return ret;
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ident0 = V3D_READ(V3D_HUB_IDENT0);
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ident1 = V3D_READ(V3D_HUB_IDENT1);
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ident2 = V3D_READ(V3D_HUB_IDENT2);
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ident3 = V3D_READ(V3D_HUB_IDENT3);
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cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
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seq_printf(m, "Revision: %d.%d.%d.%d\n",
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V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
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V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
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V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
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V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
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seq_printf(m, "MMU: %s\n",
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(ident2 & V3D_HUB_IDENT2_WITH_MMU) ? "yes" : "no");
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seq_printf(m, "TFU: %s\n",
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(ident1 & V3D_HUB_IDENT1_WITH_TFU) ? "yes" : "no");
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seq_printf(m, "TSY: %s\n",
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(ident1 & V3D_HUB_IDENT1_WITH_TSY) ? "yes" : "no");
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seq_printf(m, "MSO: %s\n",
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(ident1 & V3D_HUB_IDENT1_WITH_MSO) ? "yes" : "no");
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seq_printf(m, "L3C: %s (%dkb)\n",
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(ident1 & V3D_HUB_IDENT1_WITH_L3C) ? "yes" : "no",
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V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
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for (core = 0; core < cores; core++) {
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u32 misccfg;
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u32 nslc, ntmu, qups;
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ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
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ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
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ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
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misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
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nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
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ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
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qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
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seq_printf(m, "Core %d:\n", core);
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seq_printf(m, " Revision: %d.%d\n",
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V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
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V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
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seq_printf(m, " Slices: %d\n", nslc);
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seq_printf(m, " TMUs: %d\n", nslc * ntmu);
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seq_printf(m, " QPUs: %d\n", nslc * qups);
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seq_printf(m, " Semaphores: %d\n",
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V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
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seq_printf(m, " BCG int: %d\n",
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(ident2 & V3D_IDENT2_BCG_INT) != 0);
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seq_printf(m, " Override TMU: %d\n",
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(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
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}
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pm_runtime_mark_last_busy(v3d->dev);
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pm_runtime_put_autosuspend(v3d->dev);
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return 0;
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}
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static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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mutex_lock(&v3d->bo_lock);
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seq_printf(m, "allocated bos: %d\n",
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v3d->bo_stats.num_allocated);
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seq_printf(m, "allocated bo size (kb): %ld\n",
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(long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
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mutex_unlock(&v3d->bo_lock);
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return 0;
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}
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static int v3d_measure_clock(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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uint32_t cycles;
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int core = 0;
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int measure_ms = 1000;
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int ret;
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ret = pm_runtime_get_sync(v3d->dev);
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if (ret < 0)
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return ret;
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if (v3d->ver >= 40) {
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
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V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
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V3D_PCTR_S0));
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
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} else {
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V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
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V3D_PCTR_CYCLE_COUNT);
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V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
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V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
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V3D_V3_PCTR_0_EN_ENABLE |
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1);
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}
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msleep(measure_ms);
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cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
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seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
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cycles,
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cycles / (measure_ms * 1000),
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(cycles / (measure_ms * 100)) % 10);
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pm_runtime_mark_last_busy(v3d->dev);
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pm_runtime_put_autosuspend(v3d->dev);
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return 0;
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}
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static const struct drm_info_list v3d_debugfs_list[] = {
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{"v3d_ident", v3d_v3d_debugfs_ident, 0},
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{"v3d_regs", v3d_v3d_debugfs_regs, 0},
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{"measure_clock", v3d_measure_clock, 0},
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{"bo_stats", v3d_debugfs_bo_stats, 0},
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};
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int
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v3d_debugfs_init(struct drm_minor *minor)
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{
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return drm_debugfs_create_files(v3d_debugfs_list,
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ARRAY_SIZE(v3d_debugfs_list),
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minor->debugfs_root, minor);
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}
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