Vandita Kulkarni 960e9836f7 drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl ... Latency programming remains same as that of ICL and setting latency otimization for PCS_DW1 lanes is same as that of EHL, hence extending it to TGL. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-3-vandita.kulkarni@intel.com		2019-08-08 18:37:50 +05:30
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drm	drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl	2019-08-08 18:37:50 +05:30
host1x	drm/tegra: Changes for v5.3-rc1	2019-06-25 12:59:43 +10:00
ipu-v3	drm main pull request for v5.3-rc1 (sans mm changes)	2019-07-15 19:04:27 -07:00
vga	topic/remove-fbcon-notifiers:	2019-06-26 12:26:34 +02:00
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