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This is intended for Kernel hackers audience. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>
94 lines
4.3 KiB
ReStructuredText
94 lines
4.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=====================================
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GENERIC SYSTEM INTERCONNECT SUBSYSTEM
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=====================================
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Introduction
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------------
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This framework is designed to provide a standard kernel interface to control
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the settings of the interconnects on an SoC. These settings can be throughput,
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latency and priority between multiple interconnected devices or functional
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blocks. This can be controlled dynamically in order to save power or provide
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maximum performance.
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The interconnect bus is hardware with configurable parameters, which can be
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set on a data path according to the requests received from various drivers.
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An example of interconnect buses are the interconnects between various
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components or functional blocks in chipsets. There can be multiple interconnects
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on an SoC that can be multi-tiered.
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Below is a simplified diagram of a real-world SoC interconnect bus topology.
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::
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+----------------+ +----------------+
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| HW Accelerator |--->| M NoC |<---------------+
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+----------------+ +----------------+ |
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| | +------------+
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+-----+ +-------------+ V +------+ | |
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| DDR | | +--------+ | PCIe | | |
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+-----+ | | Slaves | +------+ | |
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^ ^ | +--------+ | | C NoC |
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| | V V | |
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+------------------+ +------------------------+ | | +-----+
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| |-->| |-->| |-->| CPU |
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| |-->| |<--| | +-----+
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| Mem NoC | | S NoC | +------------+
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| |<--| |---------+ |
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| |<--| |<------+ | | +--------+
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+------------------+ +------------------------+ | | +-->| Slaves |
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^ ^ ^ ^ ^ | | +--------+
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| | | | | | V
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+------+ | +-----+ +-----+ +---------+ +----------------+ +--------+
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| CPUs | | | GPU | | DSP | | Masters |-->| P NoC |-->| Slaves |
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+------+ | +-----+ +-----+ +---------+ +----------------+ +--------+
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+-------+
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| Modem |
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+-------+
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Terminology
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-----------
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Interconnect provider is the software definition of the interconnect hardware.
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The interconnect providers on the above diagram are M NoC, S NoC, C NoC, P NoC
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and Mem NoC.
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Interconnect node is the software definition of the interconnect hardware
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port. Each interconnect provider consists of multiple interconnect nodes,
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which are connected to other SoC components including other interconnect
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providers. The point on the diagram where the CPUs connect to the memory is
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called an interconnect node, which belongs to the Mem NoC interconnect provider.
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Interconnect endpoints are the first or the last element of the path. Every
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endpoint is a node, but not every node is an endpoint.
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Interconnect path is everything between two endpoints including all the nodes
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that have to be traversed to reach from a source to destination node. It may
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include multiple master-slave pairs across several interconnect providers.
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Interconnect consumers are the entities which make use of the data paths exposed
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by the providers. The consumers send requests to providers requesting various
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throughput, latency and priority. Usually the consumers are device drivers, that
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send request based on their needs. An example for a consumer is a video decoder
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that supports various formats and image sizes.
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Interconnect providers
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----------------------
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Interconnect provider is an entity that implements methods to initialize and
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configure interconnect bus hardware. The interconnect provider drivers should
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be registered with the interconnect provider core.
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.. kernel-doc:: include/linux/interconnect-provider.h
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Interconnect consumers
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----------------------
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Interconnect consumers are the clients which use the interconnect APIs to
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get paths between endpoints and set their bandwidth/latency/QoS requirements
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for these interconnect paths. These interfaces are not currently
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documented.
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