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9569dae75f
Split off Orion GPIO handling code into plat-orion/, and add support for multiple sets of (32) GPIO pins. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
168 lines
6.6 KiB
C
168 lines
6.6 KiB
C
/*
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* arch/arm/mach-orion5x/include/mach/orion5x.h
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*
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* Generic definitions of Orion SoC flavors:
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* Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION5X_H
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#define __ASM_ARCH_ORION5X_H
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/*****************************************************************************
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* Orion Address Maps
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*
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* phys
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* e0000000 PCIe MEM space
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* e8000000 PCI MEM space
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* f0000000 PCIe WA space (Orion-1/Orion-NAS only)
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* f1000000 on-chip peripheral registers
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* f2000000 PCIe I/O space
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* f2100000 PCI I/O space
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* f4000000 device bus mappings (boot)
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* fa000000 device bus mappings (cs0)
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* fa800000 device bus mappings (cs2)
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* fc000000 device bus mappings (cs0/cs1)
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*
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* virt phys size
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* fdd00000 f1000000 1M on-chip peripheral registers
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* fde00000 f2000000 1M PCIe I/O space
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* fdf00000 f2100000 1M PCI I/O space
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* fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
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****************************************************************************/
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#define ORION5X_REGS_PHYS_BASE 0xf1000000
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#define ORION5X_REGS_VIRT_BASE 0xfdd00000
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#define ORION5X_REGS_SIZE SZ_1M
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#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
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#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
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#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
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#define ORION5X_PCIE_IO_SIZE SZ_1M
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#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
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#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
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#define ORION5X_PCI_IO_BUS_BASE 0x00100000
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#define ORION5X_PCI_IO_SIZE SZ_1M
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/* Relevant only for Orion-1/Orion-NAS */
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#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
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#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
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#define ORION5X_PCIE_WA_SIZE SZ_16M
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#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
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#define ORION5X_PCIE_MEM_SIZE SZ_128M
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#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
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#define ORION5X_PCI_MEM_SIZE SZ_128M
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/*******************************************************************************
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* Supported Devices & Revisions
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******************************************************************************/
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/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
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#define MV88F5181_DEV_ID 0x5181
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#define MV88F5181_REV_B1 3
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#define MV88F5181L_REV_A0 8
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#define MV88F5181L_REV_A1 9
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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#define MV88F5281_REV_D0 4
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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/* Orion-1-90 (88F6183) */
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#define MV88F6183_DEV_ID 0x6183
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#define MV88F6183_REV_B0 3
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/*******************************************************************************
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* Orion Registers Map
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******************************************************************************/
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#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
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#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
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#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
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#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
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#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
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#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
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#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
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#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
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#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
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#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
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#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
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#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
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#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
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#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
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#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
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#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
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#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
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#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
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#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
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#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
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#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
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#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
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#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
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#define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x))
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#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
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#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
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#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
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#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
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#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
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#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
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#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
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#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
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#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
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/*******************************************************************************
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* Device Bus Registers
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******************************************************************************/
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#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
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#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
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#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
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#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
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#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
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#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
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#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
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#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
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#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
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#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
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#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
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#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
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#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
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#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
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#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
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/***************************************************************************
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* Orion CPU Bridge Registers
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**************************************************************************/
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#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
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#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
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#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
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#define WDT_RESET 0x0002
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#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
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#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
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#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
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#define WDT_INT_REQ 0x0008
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#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
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#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
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#endif
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