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Proviously we would only restart the FEC when PHY link or duplex state changed. PHY does not always bring down the link for speed changes, in which case we would not detect any change and keep FEC running. Switching link speed without restarting the FEC results in the FEC being stuck in an indefinite state, generating error conditions for every packet. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
272 lines
10 KiB
C
272 lines
10 KiB
C
/****************************************************************************/
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/*
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* fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
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* processors.
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*
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* (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000-2001, Lineo (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef FEC_H
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#define FEC_H
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/****************************************************************************/
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#include <linux/clocksource.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
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defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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/*
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* Just figures, Motorola would have to change the offsets for
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* registers in the same peripheral device on different models
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* of the ColdFire!
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*/
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#define FEC_IEVENT 0x004 /* Interrupt event reg */
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#define FEC_IMASK 0x008 /* Interrupt mask reg */
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#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
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#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
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#define FEC_ECNTRL 0x024 /* Ethernet control reg */
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#define FEC_MII_DATA 0x040 /* MII manage frame reg */
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#define FEC_MII_SPEED 0x044 /* MII speed control reg */
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#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
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#define FEC_R_CNTRL 0x084 /* Receive control reg */
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#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
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#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
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#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
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#define FEC_OPD 0x0ec /* Opcode + Pause duration */
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#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
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#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
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#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
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#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
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#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
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#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
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#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
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#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
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#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
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#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
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#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
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#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
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#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
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#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
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#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
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#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
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#define BM_MIIGSK_CFGR_MII 0x00
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#define BM_MIIGSK_CFGR_RMII 0x01
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#define BM_MIIGSK_CFGR_FRCONT_10M 0x40
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#else
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#define FEC_ECNTRL 0x000 /* Ethernet control reg */
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#define FEC_IEVENT 0x004 /* Interrupt even reg */
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#define FEC_IMASK 0x008 /* Interrupt mask reg */
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#define FEC_IVEC 0x00c /* Interrupt vec status reg */
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#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
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#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
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#define FEC_MII_DATA 0x040 /* MII manage frame reg */
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#define FEC_MII_SPEED 0x044 /* MII speed control reg */
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#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
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#define FEC_R_FSTART 0x090 /* FIFO receive start reg */
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#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
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#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
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#define FEC_R_CNTRL 0x104 /* Receive control reg */
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#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
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#define FEC_X_CNTRL 0x144 /* Transmit Control reg */
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#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
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#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
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#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
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#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
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#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
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#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
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#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
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#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
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#endif /* CONFIG_M5272 */
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/*
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* Define the buffer descriptor structure.
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*/
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#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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struct bufdesc {
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unsigned short cbd_datlen; /* Data length */
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unsigned short cbd_sc; /* Control and status info */
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unsigned long cbd_bufaddr; /* Buffer address */
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};
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#else
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struct bufdesc {
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unsigned short cbd_sc; /* Control and status info */
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unsigned short cbd_datlen; /* Data length */
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unsigned long cbd_bufaddr; /* Buffer address */
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};
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#endif
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struct bufdesc_ex {
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struct bufdesc desc;
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unsigned long cbd_esc;
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unsigned long cbd_prot;
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unsigned long cbd_bdu;
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unsigned long ts;
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unsigned short res0[4];
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};
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/*
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* The following definitions courtesy of commproc.h, which where
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
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*/
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#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* ?? */
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/* Buffer descriptor control/status used by Ethernet receive.
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*/
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#define BD_ENET_RX_EMPTY ((ushort)0x8000)
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#define BD_ENET_RX_WRAP ((ushort)0x2000)
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#define BD_ENET_RX_INTR ((ushort)0x1000)
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#define BD_ENET_RX_LAST ((ushort)0x0800)
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#define BD_ENET_RX_FIRST ((ushort)0x0400)
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#define BD_ENET_RX_MISS ((ushort)0x0100)
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#define BD_ENET_RX_LG ((ushort)0x0020)
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#define BD_ENET_RX_NO ((ushort)0x0010)
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#define BD_ENET_RX_SH ((ushort)0x0008)
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#define BD_ENET_RX_CR ((ushort)0x0004)
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#define BD_ENET_RX_OV ((ushort)0x0002)
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#define BD_ENET_RX_CL ((ushort)0x0001)
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#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
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/* Buffer descriptor control/status used by Ethernet transmit.
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*/
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#define BD_ENET_TX_READY ((ushort)0x8000)
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#define BD_ENET_TX_PAD ((ushort)0x4000)
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#define BD_ENET_TX_WRAP ((ushort)0x2000)
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#define BD_ENET_TX_INTR ((ushort)0x1000)
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#define BD_ENET_TX_LAST ((ushort)0x0800)
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#define BD_ENET_TX_TC ((ushort)0x0400)
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#define BD_ENET_TX_DEF ((ushort)0x0200)
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#define BD_ENET_TX_HB ((ushort)0x0100)
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#define BD_ENET_TX_LC ((ushort)0x0080)
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#define BD_ENET_TX_RL ((ushort)0x0040)
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#define BD_ENET_TX_RCMASK ((ushort)0x003c)
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#define BD_ENET_TX_UN ((ushort)0x0002)
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#define BD_ENET_TX_CSL ((ushort)0x0001)
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#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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/*enhanced buffer desciptor control/status used by Ethernet transmit*/
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#define BD_ENET_TX_INT 0x40000000
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#define BD_ENET_TX_TS 0x20000000
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/* This device has up to three irqs on some platforms */
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#define FEC_IRQ_NUM 3
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/* The number of Tx and Rx buffers. These are allocated from the page
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* pool. The code may assume these are power of two, so it it best
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* to keep them that size.
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* We don't need to allocate pages for the transmitter. We just use
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* the skbuffer directly.
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*/
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#define FEC_ENET_RX_PAGES 8
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#define FEC_ENET_RX_FRSIZE 2048
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#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
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#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
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#define FEC_ENET_TX_FRSIZE 2048
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#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
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#define TX_RING_SIZE 16 /* Must be power of two */
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#define TX_RING_MOD_MASK 15 /* for this to work */
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#define BD_ENET_RX_INT 0x00800000
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#define BD_ENET_RX_PTP ((ushort)0x0400)
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/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
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* tx_bd_base always point to the base of the buffer descriptors. The
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* cur_rx and cur_tx point to the currently available buffer.
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* The dirty_tx tracks the current buffer that is being sent by the
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* controller. The cur_tx and dirty_tx are equal under both completely
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* empty and completely full conditions. The empty/ready indicator in
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* the buffer descriptor determines the actual condition.
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*/
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struct fec_enet_private {
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/* Hardware registers of the FEC device */
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void __iomem *hwp;
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struct net_device *netdev;
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struct clk *clk_ipg;
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struct clk *clk_ahb;
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struct clk *clk_ptp;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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unsigned char *tx_bounce[TX_RING_SIZE];
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struct sk_buff *tx_skbuff[TX_RING_SIZE];
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struct sk_buff *rx_skbuff[RX_RING_SIZE];
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/* CPM dual port RAM relative addresses */
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dma_addr_t bd_dma;
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/* Address of Rx and Tx buffers */
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struct bufdesc *rx_bd_base;
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struct bufdesc *tx_bd_base;
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/* The next free ring entry */
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struct bufdesc *cur_rx, *cur_tx;
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/* The ring entries to be free()ed */
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struct bufdesc *dirty_tx;
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/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
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spinlock_t hw_lock;
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struct platform_device *pdev;
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int opened;
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int dev_id;
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/* Phylib and MDIO interface */
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struct mii_bus *mii_bus;
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struct phy_device *phy_dev;
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int mii_timeout;
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uint phy_speed;
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phy_interface_t phy_interface;
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int link;
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int full_duplex;
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int speed;
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struct completion mdio_done;
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int irq[FEC_IRQ_NUM];
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int bufdesc_ex;
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int pause_flag;
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struct napi_struct napi;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_caps;
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unsigned long last_overflow_check;
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spinlock_t tmreg_lock;
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struct cyclecounter cc;
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struct timecounter tc;
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int rx_hwtstamp_filter;
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u32 base_incval;
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u32 cycle_speed;
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int hwts_rx_en;
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int hwts_tx_en;
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struct timer_list time_keep;
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};
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void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev);
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void fec_ptp_start_cyclecounter(struct net_device *ndev);
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int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);
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/****************************************************************************/
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#endif /* FEC_H */
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