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8863057540
With disabling combine mode, the multiple successive FIFO registers or non successive FIFO registers of SAI module can work with the sdma multi fifo script. This patch is to configure the necessary information to the SDMA engine driver for support multi fifo script. 'words_per_fifo' is the channels for each dataline 'n_fifos_src' and 'n_fifos_dst' are the fifo number 'stride_fifos_src' and 'stride_fifos_dst' are the stride between enable FIFOs 'maxburst' is the multiply of datalines Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1661218573-2154-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
312 lines
11 KiB
C
312 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_SAI_H
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#define __FSL_SAI_H
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#include <linux/dma/imx-dma.h>
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#include <sound/dmaengine_pcm.h>
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#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
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SNDRV_PCM_FMTBIT_S20_3LE |\
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SNDRV_PCM_FMTBIT_S24_LE |\
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SNDRV_PCM_FMTBIT_S32_LE |\
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SNDRV_PCM_FMTBIT_DSD_U8 |\
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SNDRV_PCM_FMTBIT_DSD_U16_LE |\
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SNDRV_PCM_FMTBIT_DSD_U32_LE)
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/* SAI Register Map Register */
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#define FSL_SAI_VERID 0x00 /* SAI Version ID Register */
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#define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */
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#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
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#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
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#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
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#define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
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#define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
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#define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
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#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
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#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
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#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
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#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
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#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
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#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
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#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
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#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
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#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
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#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
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#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
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#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
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#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
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#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
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#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
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#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
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#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
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#define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */
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#define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */
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#define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
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#define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */
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#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
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#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
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#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
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#define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
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#define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
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#define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
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#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
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#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
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#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
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#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
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#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
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#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
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#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
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#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
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#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
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#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
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#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
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#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
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#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
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#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
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#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
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#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
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#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
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#define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */
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#define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */
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#define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
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#define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */
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#define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */
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#define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */
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#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
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#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
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#define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
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#define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
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#define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
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#define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
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#define FSL_SAI_xDR0(tx) (tx ? FSL_SAI_TDR0 : FSL_SAI_RDR0)
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#define FSL_SAI_xFR0(tx) (tx ? FSL_SAI_TFR0 : FSL_SAI_RFR0)
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#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
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/* SAI Transmit/Receive Control Register */
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#define FSL_SAI_CSR_TERE BIT(31)
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#define FSL_SAI_CSR_SE BIT(30)
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#define FSL_SAI_CSR_FR BIT(25)
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#define FSL_SAI_CSR_SR BIT(24)
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#define FSL_SAI_CSR_xF_SHIFT 16
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#define FSL_SAI_CSR_xF_W_SHIFT 18
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#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
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#define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
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#define FSL_SAI_CSR_WSF BIT(20)
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#define FSL_SAI_CSR_SEF BIT(19)
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#define FSL_SAI_CSR_FEF BIT(18)
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#define FSL_SAI_CSR_FWF BIT(17)
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#define FSL_SAI_CSR_FRF BIT(16)
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#define FSL_SAI_CSR_xIE_SHIFT 8
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#define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
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#define FSL_SAI_CSR_WSIE BIT(12)
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#define FSL_SAI_CSR_SEIE BIT(11)
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#define FSL_SAI_CSR_FEIE BIT(10)
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#define FSL_SAI_CSR_FWIE BIT(9)
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#define FSL_SAI_CSR_FRIE BIT(8)
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#define FSL_SAI_CSR_FRDE BIT(0)
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/* SAI Transmit and Receive Configuration 1 Register */
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#define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
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/* SAI Transmit and Receive Configuration 2 Register */
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#define FSL_SAI_CR2_SYNC BIT(30)
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#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
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#define FSL_SAI_CR2_MSEL_BUS 0
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#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
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#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
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#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
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#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
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#define FSL_SAI_CR2_BCP BIT(25)
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#define FSL_SAI_CR2_BCD_MSTR BIT(24)
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#define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */
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#define FSL_SAI_CR2_DIV_MASK 0xff
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/* SAI Transmit and Receive Configuration 3 Register */
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#define FSL_SAI_CR3_TRCE(x) ((x) << 16)
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#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
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#define FSL_SAI_CR3_WDFL(x) (x)
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#define FSL_SAI_CR3_WDFL_MASK 0x1f
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/* SAI Transmit and Receive Configuration 4 Register */
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#define FSL_SAI_CR4_FCONT BIT(28)
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#define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
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#define FSL_SAI_CR4_FCOMB_SOFT BIT(27)
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#define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26)
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#define FSL_SAI_CR4_FPACK_8 (0x2 << 24)
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#define FSL_SAI_CR4_FPACK_16 (0x3 << 24)
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#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
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#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
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#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
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#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
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#define FSL_SAI_CR4_CHMOD BIT(5)
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#define FSL_SAI_CR4_CHMOD_MASK BIT(5)
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#define FSL_SAI_CR4_MF BIT(4)
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#define FSL_SAI_CR4_FSE BIT(3)
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#define FSL_SAI_CR4_FSP BIT(1)
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#define FSL_SAI_CR4_FSD_MSTR BIT(0)
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/* SAI Transmit and Receive Configuration 5 Register */
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#define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
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#define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
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#define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
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#define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
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#define FSL_SAI_CR5_FBT(x) ((x) << 8)
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#define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
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/* SAI MCLK Control Register */
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#define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
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#define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
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#define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
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#define FSL_SAI_MCTL_MSEL_BUS 0
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#define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
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#define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
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#define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
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#define FSL_SAI_MCTL_DIV_EN BIT(23)
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#define FSL_SAI_MCTL_DIV_MASK 0xFF
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/* SAI VERID Register */
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#define FSL_SAI_VERID_MAJOR_SHIFT 24
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#define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24)
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#define FSL_SAI_VERID_MINOR_SHIFT 16
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#define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16)
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#define FSL_SAI_VERID_FEATURE_SHIFT 0
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#define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0)
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#define FSL_SAI_VERID_EFIFO_EN BIT(0)
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#define FSL_SAI_VERID_TSTMP_EN BIT(1)
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/* SAI PARAM Register */
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#define FSL_SAI_PARAM_SPF_SHIFT 16
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#define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16)
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#define FSL_SAI_PARAM_WPF_SHIFT 8
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#define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8)
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#define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0)
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/* SAI MCLK Divide Register */
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#define FSL_SAI_MDIV_MASK 0xFFFFF
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/* SAI timestamp and bitcounter */
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#define FSL_SAI_xTCTL_TSEN BIT(0)
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#define FSL_SAI_xTCTL_TSINC BIT(1)
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#define FSL_SAI_xTCTL_RTSC BIT(8)
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#define FSL_SAI_xTCTL_RBC BIT(9)
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/* SAI type */
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#define FSL_SAI_DMA BIT(0)
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#define FSL_SAI_USE_AC97 BIT(1)
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#define FSL_SAI_NET BIT(2)
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#define FSL_SAI_TRA_SYN BIT(3)
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#define FSL_SAI_REC_SYN BIT(4)
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#define FSL_SAI_USE_I2S_SLAVE BIT(5)
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/* SAI clock sources */
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#define FSL_SAI_CLK_BUS 0
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#define FSL_SAI_CLK_MAST1 1
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#define FSL_SAI_CLK_MAST2 2
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#define FSL_SAI_CLK_MAST3 3
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#define FSL_SAI_MCLK_MAX 4
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/* SAI data transfer numbers per DMA request */
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#define FSL_SAI_MAXBURST_TX 6
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#define FSL_SAI_MAXBURST_RX 6
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#define PMQOS_CPU_LATENCY BIT(0)
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/* Max number of dataline */
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#define FSL_SAI_DL_NUM (8)
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/* default dataline type is zero */
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#define FSL_SAI_DL_DEFAULT (0)
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#define FSL_SAI_DL_I2S BIT(0)
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#define FSL_SAI_DL_PDM BIT(1)
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struct fsl_sai_soc_data {
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bool use_imx_pcm;
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bool use_edma;
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bool mclk0_is_mclk1;
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unsigned int fifo_depth;
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unsigned int pins;
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unsigned int reg_offset;
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unsigned int flags;
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unsigned int max_register;
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};
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/**
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* struct fsl_sai_verid - version id data
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* @version: version number
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* @feature: feature specification number
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* 0000000000000000b - Standard feature set
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* 0000000000000000b - Standard feature set
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*/
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struct fsl_sai_verid {
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u32 version;
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u32 feature;
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};
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/**
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* struct fsl_sai_param - parameter data
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* @slot_num: The maximum number of slots per frame
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* @fifo_depth: The number of words in each FIFO (depth)
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* @dataline: The number of datalines implemented
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*/
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struct fsl_sai_param {
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u32 slot_num;
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u32 fifo_depth;
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u32 dataline;
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};
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struct fsl_sai_dl_cfg {
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unsigned int type;
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unsigned int pins[2];
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unsigned int mask[2];
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unsigned int start_off[2];
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unsigned int next_off[2];
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};
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struct fsl_sai {
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struct platform_device *pdev;
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struct regmap *regmap;
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struct clk *bus_clk;
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struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
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struct clk *pll8k_clk;
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struct clk *pll11k_clk;
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struct resource *res;
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bool is_consumer_mode;
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bool is_lsb_first;
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bool is_dsp_mode;
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bool is_pdm_mode;
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bool is_multi_fifo_dma;
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bool synchronous[2];
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struct fsl_sai_dl_cfg *dl_cfg;
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unsigned int dl_cfg_cnt;
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unsigned int mclk_id[2];
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unsigned int mclk_streams;
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unsigned int slots;
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unsigned int slot_width;
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unsigned int bclk_ratio;
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const struct fsl_sai_soc_data *soc_data;
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struct snd_soc_dai_driver cpu_dai_drv;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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struct fsl_sai_verid verid;
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struct fsl_sai_param param;
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struct pm_qos_request pm_qos_req;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_state;
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struct sdma_peripheral_config audio_config[2];
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};
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#define TX 1
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#define RX 0
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#endif /* __FSL_SAI_H */
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