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On newer Ingenic SoCs the interrupt controller supports more than 32 interrupts, which it does by duplicating the registers at intervals of 0x20 bytes within its address space. Add support for an arbitrary number of interrupts using multiple generic chips, and provide the number of chips to register from the interrupt controller probe function. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10141/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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.. | ||
board-qi_lb60.c | ||
clock-debugfs.c | ||
clock.c | ||
clock.h | ||
gpio.c | ||
irq.c | ||
irq.h | ||
Kconfig | ||
Makefile | ||
Platform | ||
platform.c | ||
pm.c | ||
prom.c | ||
reset.c | ||
reset.h | ||
serial.c | ||
serial.h | ||
setup.c | ||
time.c | ||
timer.c |