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1e4f63aecb
In the process of modifying a cpufreq policy, the cpufreq core makes
a copy of it including all of the internals which is stored on the
CPU stack. Because struct cpufreq_policy is relatively large, this
may cause the size of the stack frame to exceed the 2 KB limit and
so the GCC complains when -Wframe-larger-than= is used.
In fact, it is not necessary to copy the entire policy structure
in order to modify it, however.
First, because cpufreq_set_policy() obtains the min and max policy
limits from frequency QoS now, it is not necessary to pass the limits
to it from the callers. The only things that need to be passed to it
from there are the new governor pointer or (if there is a built-in
governor in the driver) the "policy" value representing the governor
choice. They both can be passed as individual arguments, though, so
make cpufreq_set_policy() take them this way and rework its callers
accordingly. This avoids making copies of cpufreq policies in the
callers of cpufreq_set_policy().
Second, cpufreq_set_policy() still needs to pass the new policy
data to the ->verify() callback of the cpufreq driver whose task
is to sanitize the min and max policy limits. It still does not
need to make a full copy of struct cpufreq_policy for this purpose,
but it needs to pass a few items from it to the driver in case they
are needed (different drivers have different needs in that respect
and all of them have to be covered). For this reason, introduce
struct cpufreq_policy_data to hold copies of the members of
struct cpufreq_policy used by the existing ->verify() driver
callbacks and pass a pointer to a temporary structure of that
type to ->verify() (instead of passing a pointer to full struct
cpufreq_policy to it).
While at it, notice that intel_pstate and longrun don't really need
to verify the "policy" value in struct cpufreq_policy, so drop those
check from them to avoid copying "policy" into struct
cpufreq_policy_data (which allows it to be slightly smaller).
Also while at it fix up white space in a couple of places and make
cpufreq_set_policy() static (as it can be so).
Fixes: 3000ce3c52 ("cpufreq: Use per-policy frequency QoS")
Link: https://lore.kernel.org/linux-pm/CAMuHMdX6-jb1W8uC2_237m8ctCpsnGp=JCxqt8pCWVqNXHmkVg@mail.gmail.com
Reported-by: kbuild test robot <lkp@intel.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: 5.4+ <stable@vger.kernel.org> # 5.4+
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
439 lines
9.0 KiB
C
439 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (C) 2004-2006 Sebastian Witt <se.witt@gmx.net>
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*
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* Based upon reverse engineered information
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*
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* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#define NFORCE2_XTAL 25
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#define NFORCE2_BOOTFSB 0x48
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#define NFORCE2_PLLENABLE 0xa8
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#define NFORCE2_PLLREG 0xa4
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#define NFORCE2_PLLADR 0xa0
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#define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
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#define NFORCE2_MIN_FSB 50
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#define NFORCE2_SAFE_DISTANCE 50
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/* Delay in ms between FSB changes */
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/* #define NFORCE2_DELAY 10 */
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/*
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* nforce2_chipset:
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* FSB is changed using the chipset
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*/
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static struct pci_dev *nforce2_dev;
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/* fid:
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* multiplier * 10
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*/
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static int fid;
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/* min_fsb, max_fsb:
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* minimum and maximum FSB (= FSB at boot time)
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*/
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static int min_fsb;
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static int max_fsb;
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MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
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MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
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MODULE_LICENSE("GPL");
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module_param(fid, int, 0444);
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module_param(min_fsb, int, 0444);
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MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
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MODULE_PARM_DESC(min_fsb,
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"Minimum FSB to use, if not defined: current FSB - 50");
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/**
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* nforce2_calc_fsb - calculate FSB
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* @pll: PLL value
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*
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* Calculates FSB from PLL value
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*/
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static int nforce2_calc_fsb(int pll)
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{
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unsigned char mul, div;
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mul = (pll >> 8) & 0xff;
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div = pll & 0xff;
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if (div > 0)
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return NFORCE2_XTAL * mul / div;
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return 0;
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}
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/**
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* nforce2_calc_pll - calculate PLL value
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* @fsb: FSB
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*
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* Calculate PLL value for given FSB
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*/
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static int nforce2_calc_pll(unsigned int fsb)
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{
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unsigned char xmul, xdiv;
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unsigned char mul = 0, div = 0;
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int tried = 0;
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/* Try to calculate multiplier and divider up to 4 times */
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while (((mul == 0) || (div == 0)) && (tried <= 3)) {
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for (xdiv = 2; xdiv <= 0x80; xdiv++)
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for (xmul = 1; xmul <= 0xfe; xmul++)
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if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
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fsb + tried) {
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mul = xmul;
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div = xdiv;
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}
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tried++;
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}
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if ((mul == 0) || (div == 0))
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return -1;
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return NFORCE2_PLL(mul, div);
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}
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/**
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* nforce2_write_pll - write PLL value to chipset
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* @pll: PLL value
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*
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* Writes new FSB PLL value to chipset
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*/
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static void nforce2_write_pll(int pll)
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{
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int temp;
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/* Set the pll addr. to 0x00 */
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pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
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/* Now write the value in all 64 registers */
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for (temp = 0; temp <= 0x3f; temp++)
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pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
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}
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/**
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* nforce2_fsb_read - Read FSB
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*
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* Read FSB from chipset
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* If bootfsb != 0, return FSB at boot-time
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*/
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static unsigned int nforce2_fsb_read(int bootfsb)
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{
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struct pci_dev *nforce2_sub5;
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u32 fsb, temp = 0;
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/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
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nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
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PCI_ANY_ID, PCI_ANY_ID, NULL);
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if (!nforce2_sub5)
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return 0;
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pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
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fsb /= 1000000;
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/* Check if PLL register is already set */
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pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
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if (bootfsb || !temp)
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return fsb;
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/* Use PLL register FSB value */
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pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
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fsb = nforce2_calc_fsb(temp);
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return fsb;
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}
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/**
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* nforce2_set_fsb - set new FSB
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* @fsb: New FSB
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*
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* Sets new FSB
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*/
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static int nforce2_set_fsb(unsigned int fsb)
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{
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u32 temp = 0;
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unsigned int tfsb;
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int diff;
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int pll = 0;
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if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
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pr_err("FSB %d is out of range!\n", fsb);
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return -EINVAL;
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}
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tfsb = nforce2_fsb_read(0);
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if (!tfsb) {
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pr_err("Error while reading the FSB\n");
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return -EINVAL;
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}
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/* First write? Then set actual value */
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pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
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if (!temp) {
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pll = nforce2_calc_pll(tfsb);
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if (pll < 0)
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return -EINVAL;
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nforce2_write_pll(pll);
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}
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/* Enable write access */
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temp = 0x01;
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pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
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diff = tfsb - fsb;
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if (!diff)
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return 0;
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while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
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if (diff < 0)
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tfsb++;
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else
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tfsb--;
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/* Calculate the PLL reg. value */
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pll = nforce2_calc_pll(tfsb);
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if (pll == -1)
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return -EINVAL;
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nforce2_write_pll(pll);
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#ifdef NFORCE2_DELAY
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mdelay(NFORCE2_DELAY);
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#endif
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}
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temp = 0x40;
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pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
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return 0;
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}
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/**
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* nforce2_get - get the CPU frequency
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* @cpu: CPU number
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*
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* Returns the CPU frequency
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*/
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static unsigned int nforce2_get(unsigned int cpu)
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{
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if (cpu)
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return 0;
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return nforce2_fsb_read(0) * fid * 100;
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}
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/**
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* nforce2_target - set a new CPUFreq policy
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* @policy: new policy
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* @target_freq: the target frequency
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* @relation: how that frequency relates to achieved frequency
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* (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
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*
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* Sets a new CPUFreq policy.
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*/
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static int nforce2_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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/* unsigned long flags; */
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struct cpufreq_freqs freqs;
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unsigned int target_fsb;
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if ((target_freq > policy->max) || (target_freq < policy->min))
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return -EINVAL;
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target_fsb = target_freq / (fid * 100);
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freqs.old = nforce2_get(policy->cpu);
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freqs.new = target_fsb * fid * 100;
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if (freqs.old == freqs.new)
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return 0;
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pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
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freqs.old, freqs.new);
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cpufreq_freq_transition_begin(policy, &freqs);
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/* Disable IRQs */
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/* local_irq_save(flags); */
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if (nforce2_set_fsb(target_fsb) < 0)
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pr_err("Changing FSB to %d failed\n", target_fsb);
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else
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pr_debug("Changed FSB successfully to %d\n",
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target_fsb);
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/* Enable IRQs */
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/* local_irq_restore(flags); */
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cpufreq_freq_transition_end(policy, &freqs, 0);
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return 0;
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}
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/**
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* nforce2_verify - verifies a new CPUFreq policy
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* @policy: new policy
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*/
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static int nforce2_verify(struct cpufreq_policy_data *policy)
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{
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unsigned int fsb_pol_max;
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fsb_pol_max = policy->max / (fid * 100);
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if (policy->min < (fsb_pol_max * fid * 100))
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policy->max = (fsb_pol_max + 1) * fid * 100;
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cpufreq_verify_within_cpu_limits(policy);
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return 0;
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}
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static int nforce2_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned int fsb;
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unsigned int rfid;
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/* capability check */
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if (policy->cpu != 0)
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return -ENODEV;
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/* Get current FSB */
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fsb = nforce2_fsb_read(0);
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if (!fsb)
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return -EIO;
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/* FIX: Get FID from CPU */
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if (!fid) {
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if (!cpu_khz) {
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pr_warn("cpu_khz not set, can't calculate multiplier!\n");
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return -ENODEV;
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}
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fid = cpu_khz / (fsb * 100);
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rfid = fid % 5;
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if (rfid) {
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if (rfid > 2)
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fid += 5 - rfid;
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else
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fid -= rfid;
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}
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}
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pr_info("FSB currently at %i MHz, FID %d.%d\n",
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fsb, fid / 10, fid % 10);
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/* Set maximum FSB to FSB at boot time */
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max_fsb = nforce2_fsb_read(1);
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if (!max_fsb)
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return -EIO;
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if (!min_fsb)
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min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
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if (min_fsb < NFORCE2_MIN_FSB)
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min_fsb = NFORCE2_MIN_FSB;
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/* cpuinfo and default policy values */
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policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100;
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policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100;
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return 0;
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}
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static int nforce2_cpu_exit(struct cpufreq_policy *policy)
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{
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return 0;
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}
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static struct cpufreq_driver nforce2_driver = {
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.name = "nforce2",
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.flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
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.verify = nforce2_verify,
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.target = nforce2_target,
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.get = nforce2_get,
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.init = nforce2_cpu_init,
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.exit = nforce2_cpu_exit,
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};
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#ifdef MODULE
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static const struct pci_device_id nforce2_ids[] = {
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{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 },
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{}
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};
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MODULE_DEVICE_TABLE(pci, nforce2_ids);
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#endif
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/**
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* nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
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*
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* Detects nForce2 A2 and C1 stepping
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*
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*/
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static int nforce2_detect_chipset(void)
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{
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nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
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PCI_DEVICE_ID_NVIDIA_NFORCE2,
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PCI_ANY_ID, PCI_ANY_ID, NULL);
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if (nforce2_dev == NULL)
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return -ENODEV;
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pr_info("Detected nForce2 chipset revision %X\n",
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nforce2_dev->revision);
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pr_info("FSB changing is maybe unstable and can lead to crashes and data loss\n");
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return 0;
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}
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/**
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* nforce2_init - initializes the nForce2 CPUFreq driver
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*
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* Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
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* devices, -EINVAL on problems during initialization, and zero on
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* success.
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*/
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static int __init nforce2_init(void)
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{
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/* TODO: do we need to detect the processor? */
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/* detect chipset */
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if (nforce2_detect_chipset()) {
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pr_info("No nForce2 chipset\n");
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return -ENODEV;
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}
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return cpufreq_register_driver(&nforce2_driver);
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}
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/**
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* nforce2_exit - unregisters cpufreq module
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*
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* Unregisters nForce2 FSB change support.
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*/
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static void __exit nforce2_exit(void)
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{
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cpufreq_unregister_driver(&nforce2_driver);
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}
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module_init(nforce2_init);
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module_exit(nforce2_exit);
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