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0f3cc7cac0
Convert the Allegro DVT video IP codec text binding to Yaml. Add the converted binding to the MAINTAINERS file. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
106 lines
2.6 KiB
YAML
106 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/allegro,al5e.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allegro DVT Video IP Codecs Device Tree Bindings
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maintainers:
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- Michael Tretter <m.tretter@pengutronix.de>
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description: |-
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Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
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either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
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Each actual codec engine is controlled by a microcontroller (MCU). Host
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software uses a provided mailbox interface to communicate with the MCU. The
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MCUs share an interrupt.
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properties:
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compatible:
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oneOf:
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- items:
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- const: allegro,al5e-1.1
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- const: allegro,al5e
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- items:
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- const: allegro,al5d-1.1
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- const: allegro,al5d
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reg:
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items:
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- description: The registers
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- description: The SRAM
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reg-names:
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items:
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- const: regs
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- const: sram
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Core clock
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- description: MCU clock
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- description: Core AXI master port clock
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- description: MCU AXI master port clock
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- description: AXI4-Lite slave port clock
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clock-names:
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items:
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- const: core_clk
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- const: mcu_clk
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- const: m_axi_core_aclk
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- const: m_axi_mcu_aclk
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- const: s_axi_lite_aclk
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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additionalProperties: False
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examples:
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- |
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fpga {
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#address-cells = <2>;
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#size-cells = <2>;
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al5e: video-codec@a0009000 {
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compatible = "allegro,al5e-1.1", "allegro,al5e";
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reg = <0 0xa0009000 0 0x1000>,
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<0 0xa0000000 0 0x8000>;
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reg-names = "regs", "sram";
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interrupts = <0 96 4>;
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clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
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<&clkc 71>, <&clkc 71>, <&clkc 71>;
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clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
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"m_axi_mcu_aclk", "s_axi_lite_aclk";
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};
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};
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- |
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fpga {
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#address-cells = <2>;
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#size-cells = <2>;
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al5d: video-codec@a0029000 {
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compatible = "allegro,al5d-1.1", "allegro,al5d";
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reg = <0 0xa0029000 0 0x1000>,
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<0 0xa0020000 0 0x8000>;
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reg-names = "regs", "sram";
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interrupts = <0 96 4>;
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clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,
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<&clkc 71>, <&clkc 71>, <&clkc 71>;
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clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
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"m_axi_mcu_aclk", "s_axi_lite_aclk";
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};
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};
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...
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