Quentin Schulz 933bf364e1 clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent ... clk_cifout is derived from clk_cifout_src through an integer divider limited to 32. clk_cifout_src is a child of either cpll, gpll or npll without any possibility of a divider of any sort. The default clock parent is cpll. Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in order to find the real closest possible rate for clk_cifout and not one derived from cpll only. Cc: stable@vger.kernel.org # 4.10+ Fixes: fd8bc82933 ("clk: rockchip: fix the rk3399 cifout clock") Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2023-03-07 11:26:27 +01:00
..
clk-cpu.c	clk: rockchip: allow additional mux options for cpu-clock frequency changes	2022-11-14 15:34:18 +01:00
clk-ddr.c	clk: rockchip: Export rockchip_clk_register_ddrclk()	2020-09-22 15:16:37 +02:00
clk-half-divider.c	clk: rockchip: Demote non-conformant kernel-doc header in half-divider	2021-01-26 00:24:05 +01:00
clk-inverter.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
clk-mmc-phase.c	clk: rockchip: fix mmc get phase	2020-03-06 12:06:01 -08:00
clk-muxgrf.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
clk-pll.c	clk: rockchip: Fix memory leak in rockchip_clk_register_pll()	2022-11-23 14:51:30 +01:00
clk-px30.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3036.c	clk: rockchip: Add support for hclk_sfc on rk3036	2021-07-16 00:33:42 +02:00
clk-rk3128.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3188.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3228.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3288.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3308.c	clk: rockchip: make rk3308 ddrphy4x clock critical	2021-07-29 12:43:11 +02:00
clk-rk3328.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3368.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rk3399.c	clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent	2023-03-07 11:26:27 +01:00
clk-rk3568.c	clk: rockchip: Mark hclk_vo as critical on rk3568	2022-05-03 11:16:48 +02:00
clk-rk3588.c	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
clk-rv1108.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rv1126.c	clk: rockchip: Add clock controller support for RV1126 SoC	2022-09-23 11:15:30 +02:00
clk.c	Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into clk-next	2022-12-12 11:13:08 -08:00
clk.h	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
Kconfig	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
Makefile	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
rst-rk3588.c	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
softrst.c	clk: rockchip: add lookup table support	2022-11-14 15:35:07 +01:00