Daniel Thompson 91ef84428a irqchip/gic-v3: Reset BPR during initialization ... Currently, when running on FVP, CPU 0 boots up with its BPR changed from the reset value. This renders it impossible to (preemptively) prioritize interrupts on CPU 0. This is harmless on normal systems since Linux typically does not support preemptive interrupts. It does however cause problems in systems with additional changes (such as patches for NMI simulation). Many thanks to Andrew Thoelke for suggesting the BPR as having the potential to harm preemption. Suggested-by: Andrew Thoelke <andrew.thoelke@arm.com> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2016-09-12 19:46:19 +01:00
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asm	irqchip/gic-v3: Reset BPR during initialization	2016-09-12 19:46:19 +01:00
uapi/asm	arm64 fixes:	2016-08-06 08:58:59 -04:00