Marc Zyngier 01dc9262ff KVM: arm64: Ensure I-cache isolation between vcpus of a same VM ... It recently became apparent that the ARMv8 architecture has interesting rules regarding attributes being used when fetching instructions if the MMU is off at Stage-1. In this situation, the CPU is allowed to fetch from the PoC and allocate into the I-cache (unless the memory is mapped with the XN attribute at Stage-2). If we transpose this to vcpus sharing a single physical CPU, it is possible for a vcpu running with its MMU off to influence another vcpu running with its MMU on, as the latter is expected to fetch from the PoU (and self-patching code doesn't flush below that level). In order to solve this, reuse the vcpu-private TLB invalidation code to apply the same policy to the I-cache, nuking it every time the vcpu runs on a physical CPU that ran another vcpu of the same VM in the past. This involve renaming __kvm_tlb_flush_local_vmid() to __kvm_flush_cpu_context(), and inserting a local i-cache invalidation there. Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20210303164505.68492-1-maz@kernel.org		2021-03-09 17:58:56 +00:00
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debug-sr.c	KVM: arm64: Split hyp/debug-sr.c to VHE/nVHE	2020-07-05 18:38:25 +01:00
Makefile	KVM: arm64: Add basic hooks for injecting exceptions from EL2	2020-11-10 08:34:25 +00:00
switch.c	KVM: arm64: Make kvm_skip_instr() and co private to HYP	2020-11-10 08:34:24 +00:00
sysreg-sr.c	kvm: arm64: Remove __hyp_this_cpu_read	2020-09-30 08:33:52 +01:00
timer-sr.c	KVM: arm64: Duplicate hyp/timer-sr.c for VHE/nVHE	2020-07-05 18:38:38 +01:00
tlb.c	KVM: arm64: Ensure I-cache isolation between vcpus of a same VM	2021-03-09 17:58:56 +00:00