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ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
69 lines
1.8 KiB
ArmAsm
69 lines
1.8 KiB
ArmAsm
/* linux/arch/arm/mach-s3c2412/sleep.S
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*
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* Copyright (c) 2007 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2412 Power Manager low-level sleep support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-irq.h>
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.text
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.global s3c2412_sleep_enter
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s3c2412_sleep_enter:
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mov r0, #0 /* argument for coprocessors */
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ldr r1, =S3C2410_INTPND
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ldr r2, =S3C2410_SRCPND
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ldr r3, =S3C2410_EINTPEND
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teq r0, r0
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bl s3c2412_sleep_enter1
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teq pc, r0
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bl s3c2412_sleep_enter1
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.align 5
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/* this is called twice, first with the Z flag to ensure that the
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* instructions have been loaded into the cache, and the second
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* time to try and suspend the system.
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*/
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s3c2412_sleep_enter1:
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mcr p15, 0, r0, c7, c10, 4
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mcrne p15, 0, r0, c7, c0, 4
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/* if we return from here, it is because an interrupt was
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* active when we tried to shutdown. Try and ack the IRQ and
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* retry, as simply returning causes the system to lock.
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*/
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ldrne r9, [r1]
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strne r9, [r1]
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ldrne r9, [r2]
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strne r9, [r2]
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ldrne r9, [r3]
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strne r9, [r3]
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bne s3c2412_sleep_enter1
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ret lr
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