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ca36855ef0
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
74 lines
1.6 KiB
Plaintext
74 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*/
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/dts-v1/;
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#include "armada-388-clearfog.dtsi"
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/ {
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model = "SolidRun Clearfog Base A1";
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compatible = "solidrun,clearfog-base-a1",
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"solidrun,clearfog-a1", "marvell,armada388",
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"marvell,armada385", "marvell,armada380";
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button_0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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};
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ð1 {
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phy = <&phy1>;
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};
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&gpio0 {
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phy1_reset {
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gpio-hog;
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gpios = <19 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "phy1-reset";
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};
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};
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&mdio {
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pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>;
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phy1: ethernet-phy@1 {
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/*
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* Annoyingly, the marvell phy driver configures the LED
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* register, rather than preserving reset-loaded setting.
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* We undo that rubbish here.
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*/
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marvell,reg-init = <3 16 0 0x101e>;
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reg = <1>;
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};
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};
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&pinctrl {
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/* phy1 reset */
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clearfog_phy_pins: clearfog-phy-pins {
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marvell,pins = "mpp19";
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marvell,function = "gpio";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp44";
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marvell,function = "gpio";
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};
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};
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