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In order to support certain device features, including enabling the PTP hardware clock, the ice driver needs to control some registers on the device PHY. These registers are accessed by sending sideband messages. For some hardware, these messages must be sent over the device admin queue, while other hardware has a dedicated control queue for the sideband messages. Add the neighbor device message structure for sending a message to the neighboring device. Where supported, initialize the sideband control queue and handle cleanup. Add a wrapper function for sending sideband control queue messages that read or write a neighboring device register. Because some devices send sideband messages over the AdminQ, also increase the length of the admin queue to allow more messages to be queued up. This is important because the sideband messages add additional pressure on the AQ usage. This support will be used in following patches to enable support for CONFIG_1588_PTP_CLOCK. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Tony Brelinski <tonyx.brelinski@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
93 lines
1.5 KiB
C
93 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021, Intel Corporation. */
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#ifndef _ICE_SBQ_CMD_H_
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#define _ICE_SBQ_CMD_H_
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/* This header file defines the Sideband Queue commands, error codes and
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* descriptor format. It is shared between Firmware and Software.
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*/
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/* Sideband Queue command structure and opcodes */
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enum ice_sbq_opc {
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/* Sideband Queue commands */
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ice_sbq_opc_neigh_dev_req = 0x0C00,
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ice_sbq_opc_neigh_dev_ev = 0x0C01
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};
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/* Sideband Queue descriptor. Indirect command
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* and non posted
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*/
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struct ice_sbq_cmd_desc {
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__le16 flags;
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__le16 opcode;
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__le16 datalen;
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__le16 cmd_retval;
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/* Opaque message data */
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__le32 cookie_high;
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__le32 cookie_low;
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union {
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__le16 cmd_len;
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__le16 cmpl_len;
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} param0;
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u8 reserved[6];
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__le32 addr_high;
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__le32 addr_low;
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};
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struct ice_sbq_evt_desc {
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__le16 flags;
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__le16 opcode;
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__le16 datalen;
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__le16 cmd_retval;
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u8 data[24];
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};
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enum ice_sbq_msg_dev {
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rmn_0 = 0x02,
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rmn_1 = 0x03,
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rmn_2 = 0x04,
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cgu = 0x06
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};
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enum ice_sbq_msg_opcode {
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ice_sbq_msg_rd = 0x00,
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ice_sbq_msg_wr = 0x01
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};
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#define ICE_SBQ_MSG_FLAGS 0x40
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#define ICE_SBQ_MSG_SBE_FBE 0x0F
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struct ice_sbq_msg_req {
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u8 dest_dev;
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u8 src_dev;
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u8 opcode;
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u8 flags;
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u8 sbe_fbe;
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u8 func_id;
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__le16 msg_addr_low;
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__le32 msg_addr_high;
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__le32 data;
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};
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struct ice_sbq_msg_cmpl {
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u8 dest_dev;
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u8 src_dev;
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u8 opcode;
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u8 flags;
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__le32 data;
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};
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/* Internal struct */
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struct ice_sbq_msg_input {
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u8 dest_dev;
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u8 opcode;
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u16 msg_addr_low;
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u32 msg_addr_high;
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u32 data;
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};
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#endif /* _ICE_SBQ_CMD_H_ */
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