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Add matching PSI-L threads mapping for transmission DMA channels on the J7200 platform. Signed-off-by: Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20220919205931.8397-3-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
243 lines
5.8 KiB
C
243 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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}, \
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}
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#define PSIL_SA2UL(x, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.notdpkt = tx, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep j7200_src_ep_map[] = {
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/* PDMA_MCASP - McASP0-2 */
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PSIL_PDMA_MCASP(0x4400),
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PSIL_PDMA_MCASP(0x4401),
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PSIL_PDMA_MCASP(0x4402),
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/* PDMA_SPI_G0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0x4600),
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PSIL_PDMA_XY_PKT(0x4601),
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PSIL_PDMA_XY_PKT(0x4602),
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PSIL_PDMA_XY_PKT(0x4603),
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PSIL_PDMA_XY_PKT(0x4604),
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PSIL_PDMA_XY_PKT(0x4605),
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PSIL_PDMA_XY_PKT(0x4606),
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PSIL_PDMA_XY_PKT(0x4607),
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PSIL_PDMA_XY_PKT(0x4608),
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PSIL_PDMA_XY_PKT(0x4609),
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PSIL_PDMA_XY_PKT(0x460a),
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PSIL_PDMA_XY_PKT(0x460b),
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PSIL_PDMA_XY_PKT(0x460c),
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PSIL_PDMA_XY_PKT(0x460d),
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PSIL_PDMA_XY_PKT(0x460e),
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PSIL_PDMA_XY_PKT(0x460f),
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/* PDMA_SPI_G1 - SPI4-7 */
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PSIL_PDMA_XY_PKT(0x4610),
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PSIL_PDMA_XY_PKT(0x4611),
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PSIL_PDMA_XY_PKT(0x4612),
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PSIL_PDMA_XY_PKT(0x4613),
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PSIL_PDMA_XY_PKT(0x4614),
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PSIL_PDMA_XY_PKT(0x4615),
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PSIL_PDMA_XY_PKT(0x4616),
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PSIL_PDMA_XY_PKT(0x4617),
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PSIL_PDMA_XY_PKT(0x4618),
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PSIL_PDMA_XY_PKT(0x4619),
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PSIL_PDMA_XY_PKT(0x461a),
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PSIL_PDMA_XY_PKT(0x461b),
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PSIL_PDMA_XY_PKT(0x461c),
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PSIL_PDMA_XY_PKT(0x461d),
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PSIL_PDMA_XY_PKT(0x461e),
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PSIL_PDMA_XY_PKT(0x461f),
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/* PDMA_USART_G0 - UART0-1 */
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PSIL_PDMA_XY_PKT(0x4700),
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PSIL_PDMA_XY_PKT(0x4701),
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/* PDMA_USART_G1 - UART2-3 */
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PSIL_PDMA_XY_PKT(0x4702),
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PSIL_PDMA_XY_PKT(0x4703),
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/* PDMA_USART_G2 - UART4-9 */
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PSIL_PDMA_XY_PKT(0x4704),
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PSIL_PDMA_XY_PKT(0x4705),
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PSIL_PDMA_XY_PKT(0x4706),
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PSIL_PDMA_XY_PKT(0x4707),
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PSIL_PDMA_XY_PKT(0x4708),
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PSIL_PDMA_XY_PKT(0x4709),
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/* CPSW5 */
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PSIL_ETHERNET(0x4a00),
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/* CPSW0 */
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PSIL_ETHERNET(0x7000),
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/* MCU_PDMA_MISC_G0 - SPI0 */
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PSIL_PDMA_XY_PKT(0x7100),
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PSIL_PDMA_XY_PKT(0x7101),
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PSIL_PDMA_XY_PKT(0x7102),
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PSIL_PDMA_XY_PKT(0x7103),
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/* MCU_PDMA_MISC_G1 - SPI1-2 */
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PSIL_PDMA_XY_PKT(0x7200),
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PSIL_PDMA_XY_PKT(0x7201),
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PSIL_PDMA_XY_PKT(0x7202),
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PSIL_PDMA_XY_PKT(0x7203),
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PSIL_PDMA_XY_PKT(0x7204),
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PSIL_PDMA_XY_PKT(0x7205),
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PSIL_PDMA_XY_PKT(0x7206),
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PSIL_PDMA_XY_PKT(0x7207),
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/* MCU_PDMA_MISC_G2 - UART0 */
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PSIL_PDMA_XY_PKT(0x7300),
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/* MCU_PDMA_ADC - ADC0-1 */
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PSIL_PDMA_XY_TR(0x7400),
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PSIL_PDMA_XY_TR(0x7401),
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/* SA2UL */
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PSIL_SA2UL(0x7500, 0),
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PSIL_SA2UL(0x7501, 0),
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PSIL_SA2UL(0x7502, 0),
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PSIL_SA2UL(0x7503, 0),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep j7200_dst_ep_map[] = {
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/* PDMA_MCASP - McASP0-2 */
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PSIL_PDMA_MCASP(0xc400),
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PSIL_PDMA_MCASP(0xc401),
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PSIL_PDMA_MCASP(0xc402),
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/* PDMA_SPI_G0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0xc600),
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PSIL_PDMA_XY_PKT(0xc601),
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PSIL_PDMA_XY_PKT(0xc602),
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PSIL_PDMA_XY_PKT(0xc603),
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PSIL_PDMA_XY_PKT(0xc604),
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PSIL_PDMA_XY_PKT(0xc605),
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PSIL_PDMA_XY_PKT(0xc606),
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PSIL_PDMA_XY_PKT(0xc607),
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PSIL_PDMA_XY_PKT(0xc608),
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PSIL_PDMA_XY_PKT(0xc609),
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PSIL_PDMA_XY_PKT(0xc60a),
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PSIL_PDMA_XY_PKT(0xc60b),
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PSIL_PDMA_XY_PKT(0xc60c),
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PSIL_PDMA_XY_PKT(0xc60d),
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PSIL_PDMA_XY_PKT(0xc60e),
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PSIL_PDMA_XY_PKT(0xc60f),
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/* PDMA_SPI_G1 - SPI4-7 */
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PSIL_PDMA_XY_PKT(0xc610),
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PSIL_PDMA_XY_PKT(0xc611),
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PSIL_PDMA_XY_PKT(0xc612),
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PSIL_PDMA_XY_PKT(0xc613),
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PSIL_PDMA_XY_PKT(0xc614),
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PSIL_PDMA_XY_PKT(0xc615),
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PSIL_PDMA_XY_PKT(0xc616),
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PSIL_PDMA_XY_PKT(0xc617),
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PSIL_PDMA_XY_PKT(0xc618),
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PSIL_PDMA_XY_PKT(0xc619),
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PSIL_PDMA_XY_PKT(0xc61a),
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PSIL_PDMA_XY_PKT(0xc61b),
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PSIL_PDMA_XY_PKT(0xc61c),
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PSIL_PDMA_XY_PKT(0xc61d),
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PSIL_PDMA_XY_PKT(0xc61e),
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PSIL_PDMA_XY_PKT(0xc61f),
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/* PDMA_USART_G0 - UART0-1 */
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PSIL_PDMA_XY_PKT(0xc700),
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PSIL_PDMA_XY_PKT(0xc701),
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/* PDMA_USART_G1 - UART2-3 */
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PSIL_PDMA_XY_PKT(0xc702),
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PSIL_PDMA_XY_PKT(0xc703),
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/* PDMA_USART_G2 - UART4-9 */
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PSIL_PDMA_XY_PKT(0xc704),
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PSIL_PDMA_XY_PKT(0xc705),
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PSIL_PDMA_XY_PKT(0xc706),
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PSIL_PDMA_XY_PKT(0xc707),
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PSIL_PDMA_XY_PKT(0xc708),
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PSIL_PDMA_XY_PKT(0xc709),
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/* CPSW5 */
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PSIL_ETHERNET(0xca00),
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PSIL_ETHERNET(0xca01),
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PSIL_ETHERNET(0xca02),
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PSIL_ETHERNET(0xca03),
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PSIL_ETHERNET(0xca04),
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PSIL_ETHERNET(0xca05),
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PSIL_ETHERNET(0xca06),
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PSIL_ETHERNET(0xca07),
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/* CPSW0 */
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PSIL_ETHERNET(0xf000),
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PSIL_ETHERNET(0xf001),
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PSIL_ETHERNET(0xf002),
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PSIL_ETHERNET(0xf003),
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PSIL_ETHERNET(0xf004),
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PSIL_ETHERNET(0xf005),
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PSIL_ETHERNET(0xf006),
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PSIL_ETHERNET(0xf007),
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/* MCU_PDMA_MISC_G0 - SPI0 */
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PSIL_PDMA_XY_PKT(0xf100),
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PSIL_PDMA_XY_PKT(0xf101),
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PSIL_PDMA_XY_PKT(0xf102),
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PSIL_PDMA_XY_PKT(0xf103),
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/* MCU_PDMA_MISC_G1 - SPI1-2 */
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PSIL_PDMA_XY_PKT(0xf200),
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PSIL_PDMA_XY_PKT(0xf201),
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PSIL_PDMA_XY_PKT(0xf202),
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PSIL_PDMA_XY_PKT(0xf203),
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PSIL_PDMA_XY_PKT(0xf204),
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PSIL_PDMA_XY_PKT(0xf205),
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PSIL_PDMA_XY_PKT(0xf206),
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PSIL_PDMA_XY_PKT(0xf207),
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/* MCU_PDMA_MISC_G2 - UART0 */
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PSIL_PDMA_XY_PKT(0xf300),
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/* SA2UL */
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PSIL_SA2UL(0xf500, 1),
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PSIL_SA2UL(0xf501, 1),
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};
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struct psil_ep_map j7200_ep_map = {
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.name = "j7200",
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.src = j7200_src_ep_map,
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.src_count = ARRAY_SIZE(j7200_src_ep_map),
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.dst = j7200_dst_ep_map,
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.dst_count = ARRAY_SIZE(j7200_dst_ep_map),
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};
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