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42ae6f1695
The Ux500 is device tree-only since ages. Delete the platform data header and push it into or next to the driver instead. Drop the non-DT probe path since this will not happen. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230417-ux500-dma40-cleanup-v3-4-60bfa6785968@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef STE_DMA40_H
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#define STE_DMA40_H
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/*
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* Maxium size for a single dma descriptor
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* Size is limited to 16 bits.
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* Size is in the units of addr-widths (1,2,4,8 bytes)
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* Larger transfers will be split up to multiple linked desc
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*/
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#define STEDMA40_MAX_SEG_SIZE 0xFFFF
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/* dev types for memcpy */
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#define STEDMA40_DEV_DST_MEMORY (-1)
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#define STEDMA40_DEV_SRC_MEMORY (-1)
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enum stedma40_mode {
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STEDMA40_MODE_LOGICAL = 0,
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STEDMA40_MODE_PHYSICAL,
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STEDMA40_MODE_OPERATION,
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};
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enum stedma40_mode_opt {
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STEDMA40_PCHAN_BASIC_MODE = 0,
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STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
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STEDMA40_PCHAN_MODULO_MODE,
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STEDMA40_PCHAN_DOUBLE_DST_MODE,
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STEDMA40_LCHAN_SRC_PHY_DST_LOG,
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STEDMA40_LCHAN_SRC_LOG_DST_PHY,
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};
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#define STEDMA40_ESIZE_8_BIT 0x0
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#define STEDMA40_ESIZE_16_BIT 0x1
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#define STEDMA40_ESIZE_32_BIT 0x2
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#define STEDMA40_ESIZE_64_BIT 0x3
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/* The value 4 indicates that PEN-reg shall be set to 0 */
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#define STEDMA40_PSIZE_PHY_1 0x4
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#define STEDMA40_PSIZE_PHY_2 0x0
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#define STEDMA40_PSIZE_PHY_4 0x1
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#define STEDMA40_PSIZE_PHY_8 0x2
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#define STEDMA40_PSIZE_PHY_16 0x3
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/*
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* The number of elements differ in logical and
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* physical mode
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*/
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#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
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#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
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#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
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#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
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/* Maximum number of possible physical channels */
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#define STEDMA40_MAX_PHYS 32
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enum stedma40_flow_ctrl {
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STEDMA40_NO_FLOW_CTRL,
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STEDMA40_FLOW_CTRL,
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};
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/**
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* struct stedma40_half_channel_info - dst/src channel configuration
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*
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* @big_endian: true if the src/dst should be read as big endian
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* @data_width: Data width of the src/dst hardware
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* @p_size: Burst size
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* @flow_ctrl: Flow control on/off.
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*/
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struct stedma40_half_channel_info {
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bool big_endian;
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enum dma_slave_buswidth data_width;
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int psize;
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enum stedma40_flow_ctrl flow_ctrl;
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};
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/**
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* struct stedma40_chan_cfg - Structure to be filled by client drivers.
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*
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* @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
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* @high_priority: true if high-priority
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* @realtime: true if realtime mode is to be enabled. Only available on DMA40
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* version 3+, i.e DB8500v2+
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* @mode: channel mode: physical, logical, or operation
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* @mode_opt: options for the chosen channel mode
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* @dev_type: src/dst device type (driver uses dir to figure out which)
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* @src_info: Parameters for dst half channel
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* @dst_info: Parameters for dst half channel
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* @use_fixed_channel: if true, use physical channel specified by phy_channel
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* @phy_channel: physical channel to use, only if use_fixed_channel is true
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*
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* This structure has to be filled by the client drivers.
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* It is recommended to do all dma configurations for clients in the machine.
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*
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*/
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struct stedma40_chan_cfg {
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enum dma_transfer_direction dir;
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bool high_priority;
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bool realtime;
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enum stedma40_mode mode;
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enum stedma40_mode_opt mode_opt;
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int dev_type;
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struct stedma40_half_channel_info src_info;
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struct stedma40_half_channel_info dst_info;
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bool use_fixed_channel;
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int phy_channel;
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};
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#endif /* STE_DMA40_H */
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