mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-27 13:05:03 +08:00
cac2a3552c
Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201104164923.21238-13-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
158 lines
4.6 KiB
YAML
158 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: NVIDIA Tegra124 SoC Memory Controller
|
|
|
|
maintainers:
|
|
- Jon Hunter <jonathanh@nvidia.com>
|
|
- Thierry Reding <thierry.reding@gmail.com>
|
|
|
|
description: |
|
|
Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
|
|
These are interleaved to provide high performance with the load shared across
|
|
two memory channels. The Tegra124 Memory Controller handles memory requests
|
|
from internal clients and arbitrates among them to allocate memory bandwidth
|
|
for DDR3L and LPDDR3 SDRAMs.
|
|
|
|
properties:
|
|
compatible:
|
|
const: nvidia,tegra124-mc
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
clock-names:
|
|
items:
|
|
- const: mc
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
"#reset-cells":
|
|
const: 1
|
|
|
|
"#iommu-cells":
|
|
const: 1
|
|
|
|
"#interconnect-cells":
|
|
const: 1
|
|
|
|
patternProperties:
|
|
"^emc-timings-[0-9]+$":
|
|
type: object
|
|
properties:
|
|
nvidia,ram-code:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
Value of RAM_CODE this timing set is used for.
|
|
|
|
patternProperties:
|
|
"^timing-[0-9]+$":
|
|
type: object
|
|
properties:
|
|
clock-frequency:
|
|
description:
|
|
Memory clock rate in Hz.
|
|
minimum: 1000000
|
|
maximum: 1066000000
|
|
|
|
nvidia,emem-configuration:
|
|
$ref: /schemas/types.yaml#/definitions/uint32-array
|
|
description: |
|
|
Values to be written to the EMEM register block. See section
|
|
"15.6.1 MC Registers" in the TRM.
|
|
items:
|
|
- description: MC_EMEM_ARB_CFG
|
|
- description: MC_EMEM_ARB_OUTSTANDING_REQ
|
|
- description: MC_EMEM_ARB_TIMING_RCD
|
|
- description: MC_EMEM_ARB_TIMING_RP
|
|
- description: MC_EMEM_ARB_TIMING_RC
|
|
- description: MC_EMEM_ARB_TIMING_RAS
|
|
- description: MC_EMEM_ARB_TIMING_FAW
|
|
- description: MC_EMEM_ARB_TIMING_RRD
|
|
- description: MC_EMEM_ARB_TIMING_RAP2PRE
|
|
- description: MC_EMEM_ARB_TIMING_WAP2PRE
|
|
- description: MC_EMEM_ARB_TIMING_R2R
|
|
- description: MC_EMEM_ARB_TIMING_W2W
|
|
- description: MC_EMEM_ARB_TIMING_R2W
|
|
- description: MC_EMEM_ARB_TIMING_W2R
|
|
- description: MC_EMEM_ARB_DA_TURNS
|
|
- description: MC_EMEM_ARB_DA_COVERS
|
|
- description: MC_EMEM_ARB_MISC0
|
|
- description: MC_EMEM_ARB_MISC1
|
|
- description: MC_EMEM_ARB_RING1_THROTTLE
|
|
|
|
required:
|
|
- clock-frequency
|
|
- nvidia,emem-configuration
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- nvidia,ram-code
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clocks
|
|
- clock-names
|
|
- "#reset-cells"
|
|
- "#iommu-cells"
|
|
- "#interconnect-cells"
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
memory-controller@70019000 {
|
|
compatible = "nvidia,tegra124-mc";
|
|
reg = <0x70019000 0x1000>;
|
|
clocks = <&tegra_car 32>;
|
|
clock-names = "mc";
|
|
|
|
interrupts = <0 77 4>;
|
|
|
|
#iommu-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#interconnect-cells = <1>;
|
|
|
|
emc-timings-3 {
|
|
nvidia,ram-code = <3>;
|
|
|
|
timing-12750000 {
|
|
clock-frequency = <12750000>;
|
|
|
|
nvidia,emem-configuration = <
|
|
0x40040001 /* MC_EMEM_ARB_CFG */
|
|
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
|
|
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
|
|
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
|
|
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
|
|
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
|
|
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
|
|
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
|
|
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
|
|
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
|
|
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
|
|
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
|
|
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
|
|
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
|
|
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
|
|
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
|
|
0x77e30303 /* MC_EMEM_ARB_MISC0 */
|
|
0x70000f03 /* MC_EMEM_ARB_MISC1 */
|
|
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
|
|
>;
|
|
};
|
|
};
|
|
};
|