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Microchip: A "fix" for the system controller's regs on PolarFire SoC, adding a missing reg property. The patch had been sitting there for months and I only re-found it recently, so you can guess how much of a "fix" it actually is. It'll become needed when the system controller's QSPI gets added in the future, but at present there's no urgency as the driver can handle both the current and "fixed" versions. StarFive: Basic support for the JH7110 & the associated first-party dev board, the VisionFive v2 (in two forms). There's a bunch of dt-bindings required for this too, all of which have had input from the DT folk. There's enough in this tag to boot to a console w/ an initramfs but little more. The SoC supports some of the "new" bit manipulation instructions, which is a good test for the recently added Zbb support in the kernel. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZC8o6wAKCRB4tDGHoIJi 0pdpAP0Y0qkT5tZSV635h2XOrWBpW3D3Vpx6+LGmw2mRjhHVPgD+Mfe0LkP6Dbq3 JS6fMISbgMAG/8dqcys/e0gmHksYJAk= =FsQ1 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5U/EACgkQYKtH/8kJ Uif0hhAAxHk3QfPh5BF/1TzzUdeOgXuCiT9sQWHB9VtX1N03nwRoMETbFPRxjI1v P/KckzA5nxVA8q8Me+hb5nRQFwiDOVsH5cBMMnPQ46NGImEaptZ7Jwf1/RT1yk6n eBg9vRipRhD56CYTE20iasjhwjVohljvce58Rg61oXQ2lK1dKxnIjPeDfypPz9/p 149/wWUy8e6pGIciDw25hKGuxZiXHlO4OwdL0yWggXl/iuBi8l7gAQAcCv7vWNS3 oM8t6n/o1Vr0L+MBJtBBKPmuPKu7u54+RWsaKrO3zyiRRKGjI/VMZOi5ZKcooynL ThAGlqCIrnXu25XJ2V7l95FDTdPeTljhh1FRyOIJjvzlCX9QBdr5suQU3q9zr+Mf ZdE5baezkwsTF+1Hi/Yc65gCAtUfQmGG88/TE1krFw4aaE1xVr7nAfDCpdLcCzDS D/1b9/4h/2B2dJIdBO3VdzKG4bTcaK3Eb6TX6z2zIZ6stNHcoDxr6dcQXdiGAoYu /I8zAX3zTo5Q8E0Y67h7ao4dxDqxVUIop/92OJeD3X3IkcJreXEuxBEEsRvs53P6 /tqAsG5zPpW5GwfeopUHfFUYJRn+sLrqQ9zD+k4InwiCSlR/tJ7tBMXqyRsQUEyR P336MHjq10PRVmgKjsPpTx87K9f39Qgh6doHWAKBfMo/gSQ8z9U= =l6EI -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.4 Microchip: A "fix" for the system controller's regs on PolarFire SoC, adding a missing reg property. The patch had been sitting there for months and I only re-found it recently, so you can guess how much of a "fix" it actually is. It'll become needed when the system controller's QSPI gets added in the future, but at present there's no urgency as the driver can handle both the current and "fixed" versions. StarFive: Basic support for the JH7110 & the associated first-party dev board, the VisionFive v2 (in two forms). There's a bunch of dt-bindings required for this too, all of which have had input from the DT folk. There's enough in this tag to boot to a console w/ an initramfs but little more. The SoC supports some of the "new" bit manipulation instructions, which is a good test for the recently added Zbb support in the kernel. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree riscv: dts: starfive: Add StarFive JH7110 pin function definitions riscv: dts: starfive: Add initial StarFive JH7110 device tree dt-bindings: riscv: Add SiFive S7 compatible dt-bindings: interrupt-controller: Add StarFive JH7110 plic dt-bindings: timer: Add StarFive JH7110 clint dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator riscv: dts: microchip: fix the mpfs' mailbox regs riscv: dts: microchip: add mpfs specific macb reset support Link: https://lore.kernel.org/r/20230406-shank-impromptu-3d483bbc249f@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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| linux | ||
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