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8e620b0476
On AArch64, the meaning of the XN bit has changed to UXN (user). The PXN (privileged) bit must be set to prevent kernel execution. Without the PXN bit set, the CPU may speculatively access device memory. This patch ensures that all the mappings that the kernel must not execute from (including user mappings) have the PXN bit set. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
259 lines
7.1 KiB
C
259 lines
7.1 KiB
C
/*
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* Based on arch/arm/include/asm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_IO_H
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#define __ASM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/barrier.h>
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#include <asm/pgtable.h>
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/*
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* Generic IO read/write. These perform native-endian accesses.
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*/
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
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return val;
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
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return val;
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
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return val;
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}
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 val;
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asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
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return val;
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}
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/* IO barriers */
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#define mmiowb() do { } while (0)
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
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#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
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#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
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#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access.
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
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/*
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* I/O port access primitives.
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*/
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#define IO_SPACE_LIMIT 0xffff
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#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_2M))
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static inline u8 inb(unsigned long addr)
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{
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return readb(addr + PCI_IOBASE);
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}
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static inline u16 inw(unsigned long addr)
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{
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return readw(addr + PCI_IOBASE);
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}
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static inline u32 inl(unsigned long addr)
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{
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return readl(addr + PCI_IOBASE);
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}
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static inline void outb(u8 b, unsigned long addr)
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{
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writeb(b, addr + PCI_IOBASE);
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}
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static inline void outw(u16 b, unsigned long addr)
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{
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writew(b, addr + PCI_IOBASE);
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}
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static inline void outl(u32 b, unsigned long addr)
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{
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writel(b, addr + PCI_IOBASE);
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}
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#define inb_p(addr) inb(addr)
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#define inw_p(addr) inw(addr)
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#define inl_p(addr) inl(addr)
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#define outb_p(x, addr) outb((x), (addr))
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#define outw_p(x, addr) outw((x), (addr))
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#define outl_p(x, addr) outl((x), (addr))
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static inline void insb(unsigned long addr, void *buffer, int count)
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{
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u8 *buf = buffer;
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while (count--)
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*buf++ = __raw_readb(addr + PCI_IOBASE);
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}
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static inline void insw(unsigned long addr, void *buffer, int count)
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{
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u16 *buf = buffer;
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while (count--)
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*buf++ = __raw_readw(addr + PCI_IOBASE);
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}
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static inline void insl(unsigned long addr, void *buffer, int count)
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{
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u32 *buf = buffer;
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while (count--)
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*buf++ = __raw_readl(addr + PCI_IOBASE);
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}
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static inline void outsb(unsigned long addr, const void *buffer, int count)
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{
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const u8 *buf = buffer;
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while (count--)
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__raw_writeb(*buf++, addr + PCI_IOBASE);
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}
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static inline void outsw(unsigned long addr, const void *buffer, int count)
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{
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const u16 *buf = buffer;
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while (count--)
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__raw_writew(*buf++, addr + PCI_IOBASE);
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}
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static inline void outsl(unsigned long addr, const void *buffer, int count)
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{
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const u32 *buf = buffer;
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while (count--)
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__raw_writel(*buf++, addr + PCI_IOBASE);
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}
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#define insb_p(port,to,len) insb(port,to,len)
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#define insw_p(port,to,len) insw(port,to,len)
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#define insl_p(port,to,len) insl(port,to,len)
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#define outsb_p(port,from,len) outsb(port,from,len)
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#define outsw_p(port,from,len) outsw(port,from,len)
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#define outsl_p(port,from,len) outsl(port,from,len)
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/*
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* String version of I/O memory access operations.
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*/
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extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
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extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
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extern void __memset_io(volatile void __iomem *, int, size_t);
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#define memset_io(c,v,l) __memset_io((c),(v),(l))
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#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
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#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
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/*
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* I/O memory mapping functions.
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*/
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extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
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extern void __iounmap(volatile void __iomem *addr);
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#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
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#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
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#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
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#define iounmap __iounmap
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#define ARCH_HAS_IOREMAP_WC
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#include <asm-generic/iomap.h>
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/*
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* More restrictive address range checking than the default implementation
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* (PHYS_OFFSET and PHYS_MASK taken into account).
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*/
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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extern int valid_phys_addr_range(unsigned long addr, size_t size);
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extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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extern int devmem_is_allowed(unsigned long pfn);
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_IO_H */
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