Geert Uytterhoeven 8e1c3aa30c arm64: dts: r8a7795: Add CA53 L2 cache-controller node ... Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>		2016-02-17 14:53:14 +09:00
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boot	arm64: dts: r8a7795: Add CA53 L2 cache-controller node	2016-02-17 14:53:14 +09:00
configs	Third Round of Renesas ARM64 Based SoC Defconfig Updates for v4.5	2015-12-22 12:50:29 -08:00
crypto	arm64: crypto: reduce priority of core AES cipher	2015-11-18 12:09:08 +00:00
include	dma-mapping: always provide the dma_map_ops based implementation	2016-01-20 17:09:18 -08:00
kernel	arm64: insn: remove BUG_ON from codegen	2016-01-17 19:15:26 -05:00
kvm	arm64: KVM: Add support for 16-bit VMID	2015-12-18 10:15:12 +00:00
lib	arm64: add KASAN support	2015-10-12 17:46:36 +01:00
mm	arm64, thp: remove infrastructure for handling splitting PMDs	2016-01-15 17:56:32 -08:00
net	arm64: bpf: add extra pass to handle faulty codegen	2016-01-17 19:15:26 -05:00
xen	xen/arm: introduce HYPERVISOR_platform_op on arm and arm64	2015-12-21 14:40:56 +00:00
Kconfig	dma-mapping: always provide the dma_map_ops based implementation	2016-01-20 17:09:18 -08:00
Kconfig.debug	arch: consolidate CONFIG_STRICT_DEVM in lib/Kconfig.debug	2016-01-09 06:30:49 -08:00
Kconfig.platforms	ARM: SoC support for Tegra platforms for v4.5	2016-01-22 17:30:52 -08:00
Makefile	arm64 updates for 4.4:	2015-11-04 14:47:13 -08:00