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a46cfc0f01
In preparation for switch port enumeration while also preserving the potential for multi-domain / multi-root CXL topologies. Introduce a 'struct device' generic mechanism for retrieving a root CXL port, if one is registered. Note that the only known multi-domain CXL configurations are running the cxl_test unit test on a system that also publishes an ACPI0017 device. With this in hand the nvdimm-bridge lookup can be with device_find_child() instead of bus_find_device() + custom mocked lookup infrastructure in cxl_test. The mechanism looks for a 2nd level port since the root level topology is platform-firmware specific and the 2nd level down follows standard PCIe topology expectations. The cxl_acpi 2nd level is associated with a PCIe Root Port. Reported-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164367562182.225521.9488555616768096049.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
278 lines
6.6 KiB
C
278 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. */
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/idr.h>
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#include <cxlmem.h>
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#include <cxl.h>
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#include "core.h"
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/**
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* DOC: cxl pmem
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*
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* The core CXL PMEM infrastructure supports persistent memory
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* provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
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* 'bridge' device is added at the root of a CXL device topology if
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* platform firmware advertises at least one persistent memory capable
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* CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus'
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* device. Then for each cxl_memdev in the CXL device topology a bridge
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* device is added to host a LIBNVDIMM dimm object. When these bridges
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* are registered native LIBNVDIMM uapis are translated to CXL
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* operations, for example, namespace label access commands.
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*/
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static DEFINE_IDA(cxl_nvdimm_bridge_ida);
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static void cxl_nvdimm_bridge_release(struct device *dev)
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{
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struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev);
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ida_free(&cxl_nvdimm_bridge_ida, cxl_nvb->id);
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kfree(cxl_nvb);
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}
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static const struct attribute_group *cxl_nvdimm_bridge_attribute_groups[] = {
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&cxl_base_attribute_group,
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NULL,
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};
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const struct device_type cxl_nvdimm_bridge_type = {
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.name = "cxl_nvdimm_bridge",
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.release = cxl_nvdimm_bridge_release,
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.groups = cxl_nvdimm_bridge_attribute_groups,
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};
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struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev)
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{
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if (dev_WARN_ONCE(dev, dev->type != &cxl_nvdimm_bridge_type,
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"not a cxl_nvdimm_bridge device\n"))
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return NULL;
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return container_of(dev, struct cxl_nvdimm_bridge, dev);
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}
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EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm_bridge, CXL);
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bool is_cxl_nvdimm_bridge(struct device *dev)
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{
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return dev->type == &cxl_nvdimm_bridge_type;
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}
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EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm_bridge, CXL);
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static int match_nvdimm_bridge(struct device *dev, void *data)
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{
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return is_cxl_nvdimm_bridge(dev);
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}
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_nvdimm *cxl_nvd)
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{
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struct cxl_port *port = find_cxl_root(&cxl_nvd->dev);
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struct device *dev;
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if (!port)
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return NULL;
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dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge);
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put_device(&port->dev);
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if (!dev)
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return NULL;
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return to_cxl_nvdimm_bridge(dev);
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}
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EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);
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static struct cxl_nvdimm_bridge *cxl_nvdimm_bridge_alloc(struct cxl_port *port)
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{
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct device *dev;
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int rc;
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cxl_nvb = kzalloc(sizeof(*cxl_nvb), GFP_KERNEL);
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if (!cxl_nvb)
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return ERR_PTR(-ENOMEM);
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rc = ida_alloc(&cxl_nvdimm_bridge_ida, GFP_KERNEL);
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if (rc < 0)
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goto err;
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cxl_nvb->id = rc;
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dev = &cxl_nvb->dev;
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cxl_nvb->port = port;
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cxl_nvb->state = CXL_NVB_NEW;
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device_initialize(dev);
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device_set_pm_not_required(dev);
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dev->parent = &port->dev;
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dev->bus = &cxl_bus_type;
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dev->type = &cxl_nvdimm_bridge_type;
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return cxl_nvb;
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err:
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kfree(cxl_nvb);
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return ERR_PTR(rc);
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}
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static void unregister_nvb(void *_cxl_nvb)
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{
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struct cxl_nvdimm_bridge *cxl_nvb = _cxl_nvb;
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bool flush;
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/*
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* If the bridge was ever activated then there might be in-flight state
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* work to flush. Once the state has been changed to 'dead' then no new
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* work can be queued by user-triggered bind.
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*/
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cxl_device_lock(&cxl_nvb->dev);
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flush = cxl_nvb->state != CXL_NVB_NEW;
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cxl_nvb->state = CXL_NVB_DEAD;
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cxl_device_unlock(&cxl_nvb->dev);
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/*
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* Even though the device core will trigger device_release_driver()
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* before the unregister, it does not know about the fact that
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* cxl_nvdimm_bridge_driver defers ->remove() work. So, do the driver
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* release not and flush it before tearing down the nvdimm device
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* hierarchy.
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*/
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device_release_driver(&cxl_nvb->dev);
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if (flush)
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flush_work(&cxl_nvb->state_work);
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device_unregister(&cxl_nvb->dev);
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}
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/**
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* devm_cxl_add_nvdimm_bridge() - add the root of a LIBNVDIMM topology
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* @host: platform firmware root device
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* @port: CXL port at the root of a CXL topology
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*
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* Return: bridge device that can host cxl_nvdimm objects
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*/
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struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
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struct cxl_port *port)
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{
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct device *dev;
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int rc;
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if (!IS_ENABLED(CONFIG_CXL_PMEM))
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return ERR_PTR(-ENXIO);
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cxl_nvb = cxl_nvdimm_bridge_alloc(port);
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if (IS_ERR(cxl_nvb))
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return cxl_nvb;
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dev = &cxl_nvb->dev;
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rc = dev_set_name(dev, "nvdimm-bridge%d", cxl_nvb->id);
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if (rc)
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goto err;
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rc = device_add(dev);
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if (rc)
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goto err;
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rc = devm_add_action_or_reset(host, unregister_nvb, cxl_nvb);
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if (rc)
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return ERR_PTR(rc);
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return cxl_nvb;
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err:
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put_device(dev);
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return ERR_PTR(rc);
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_nvdimm_bridge, CXL);
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static void cxl_nvdimm_release(struct device *dev)
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{
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struct cxl_nvdimm *cxl_nvd = to_cxl_nvdimm(dev);
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kfree(cxl_nvd);
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}
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static const struct attribute_group *cxl_nvdimm_attribute_groups[] = {
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&cxl_base_attribute_group,
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NULL,
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};
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const struct device_type cxl_nvdimm_type = {
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.name = "cxl_nvdimm",
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.release = cxl_nvdimm_release,
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.groups = cxl_nvdimm_attribute_groups,
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};
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bool is_cxl_nvdimm(struct device *dev)
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{
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return dev->type == &cxl_nvdimm_type;
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}
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EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm, CXL);
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struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev)
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{
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if (dev_WARN_ONCE(dev, !is_cxl_nvdimm(dev),
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"not a cxl_nvdimm device\n"))
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return NULL;
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return container_of(dev, struct cxl_nvdimm, dev);
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}
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EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm, CXL);
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static struct cxl_nvdimm *cxl_nvdimm_alloc(struct cxl_memdev *cxlmd)
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{
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struct cxl_nvdimm *cxl_nvd;
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struct device *dev;
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cxl_nvd = kzalloc(sizeof(*cxl_nvd), GFP_KERNEL);
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if (!cxl_nvd)
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return ERR_PTR(-ENOMEM);
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dev = &cxl_nvd->dev;
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cxl_nvd->cxlmd = cxlmd;
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device_initialize(dev);
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device_set_pm_not_required(dev);
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dev->parent = &cxlmd->dev;
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dev->bus = &cxl_bus_type;
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dev->type = &cxl_nvdimm_type;
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return cxl_nvd;
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}
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static void cxl_nvd_unregister(void *dev)
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{
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device_unregister(dev);
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}
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/**
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* devm_cxl_add_nvdimm() - add a bridge between a cxl_memdev and an nvdimm
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* @host: same host as @cxlmd
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* @cxlmd: cxl_memdev instance that will perform LIBNVDIMM operations
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*
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* Return: 0 on success negative error code on failure.
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*/
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int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd)
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{
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struct cxl_nvdimm *cxl_nvd;
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struct device *dev;
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int rc;
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cxl_nvd = cxl_nvdimm_alloc(cxlmd);
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if (IS_ERR(cxl_nvd))
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return PTR_ERR(cxl_nvd);
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dev = &cxl_nvd->dev;
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rc = dev_set_name(dev, "pmem%d", cxlmd->id);
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if (rc)
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goto err;
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rc = device_add(dev);
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if (rc)
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goto err;
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dev_dbg(host, "%s: register %s\n", dev_name(dev->parent),
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dev_name(dev));
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return devm_add_action_or_reset(host, cxl_nvd_unregister, dev);
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err:
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put_device(dev);
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return rc;
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_nvdimm, CXL);
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