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And use it in drivers accessing the bridge->next field directly. This is part of our attempt to make the bridge chain a double-linked list based on the generic list helpers. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191203141515.3597631-3-boris.brezillon@collabora.com
767 lines
19 KiB
C
767 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Rob Clark <rob@ti.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/sort.h>
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#include <linux/sys_soc.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_file.h>
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#include <drm/drm_ioctl.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_prime.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include "omap_dmm_tiler.h"
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#include "omap_drv.h"
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#define DRIVER_NAME MODULE_NAME
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#define DRIVER_DESC "OMAP DRM"
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#define DRIVER_DATE "20110917"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 0
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/*
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* mode config funcs
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*/
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/* Notes about mapping DSS and DRM entities:
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* CRTC: overlay
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* encoder: manager.. with some extension to allow one primary CRTC
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* and zero or more video CRTC's to be mapped to one encoder?
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* connector: dssdev.. manager can be attached/detached from different
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* devices
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*/
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static void omap_atomic_wait_for_completion(struct drm_device *dev,
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struct drm_atomic_state *old_state)
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{
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struct drm_crtc_state *new_crtc_state;
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struct drm_crtc *crtc;
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unsigned int i;
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int ret;
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for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
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if (!new_crtc_state->active)
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continue;
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ret = omap_crtc_wait_pending(crtc);
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if (!ret)
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dev_warn(dev->dev,
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"atomic complete timeout (pipe %u)!\n", i);
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}
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}
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static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = old_state->dev;
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struct omap_drm_private *priv = dev->dev_private;
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priv->dispc_ops->runtime_get(priv->dispc);
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/* Apply the atomic update. */
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drm_atomic_helper_commit_modeset_disables(dev, old_state);
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if (priv->omaprev != 0x3430) {
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/* With the current dss dispc implementation we have to enable
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* the new modeset before we can commit planes. The dispc ovl
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* configuration relies on the video mode configuration been
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* written into the HW when the ovl configuration is
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* calculated.
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*
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* This approach is not ideal because after a mode change the
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* plane update is executed only after the first vblank
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* interrupt. The dispc implementation should be fixed so that
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* it is able use uncommitted drm state information.
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*/
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drm_atomic_helper_commit_modeset_enables(dev, old_state);
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omap_atomic_wait_for_completion(dev, old_state);
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drm_atomic_helper_commit_planes(dev, old_state, 0);
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drm_atomic_helper_commit_hw_done(old_state);
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} else {
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/*
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* OMAP3 DSS seems to have issues with the work-around above,
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* resulting in endless sync losts if a crtc is enabled without
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* a plane. For now, skip the WA for OMAP3.
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*/
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drm_atomic_helper_commit_planes(dev, old_state, 0);
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drm_atomic_helper_commit_modeset_enables(dev, old_state);
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drm_atomic_helper_commit_hw_done(old_state);
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}
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/*
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* Wait for completion of the page flips to ensure that old buffers
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* can't be touched by the hardware anymore before cleaning up planes.
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*/
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omap_atomic_wait_for_completion(dev, old_state);
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drm_atomic_helper_cleanup_planes(dev, old_state);
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priv->dispc_ops->runtime_put(priv->dispc);
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}
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static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
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.atomic_commit_tail = omap_atomic_commit_tail,
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};
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static const struct drm_mode_config_funcs omap_mode_config_funcs = {
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.fb_create = omap_framebuffer_create,
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.output_poll_changed = drm_fb_helper_output_poll_changed,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static void omap_disconnect_pipelines(struct drm_device *ddev)
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{
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struct omap_drm_private *priv = ddev->dev_private;
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unsigned int i;
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for (i = 0; i < priv->num_pipes; i++) {
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struct omap_drm_pipeline *pipe = &priv->pipes[i];
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if (pipe->output->panel)
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drm_panel_detach(pipe->output->panel);
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omapdss_device_disconnect(NULL, pipe->output);
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omapdss_device_put(pipe->output);
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pipe->output = NULL;
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}
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memset(&priv->channels, 0, sizeof(priv->channels));
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priv->num_pipes = 0;
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}
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static int omap_connect_pipelines(struct drm_device *ddev)
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{
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struct omap_drm_private *priv = ddev->dev_private;
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struct omap_dss_device *output = NULL;
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int r;
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for_each_dss_output(output) {
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r = omapdss_device_connect(priv->dss, NULL, output);
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if (r == -EPROBE_DEFER) {
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omapdss_device_put(output);
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return r;
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} else if (r) {
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dev_warn(output->dev, "could not connect output %s\n",
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output->name);
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} else {
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struct omap_drm_pipeline *pipe;
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pipe = &priv->pipes[priv->num_pipes++];
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pipe->output = omapdss_device_get(output);
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if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
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/* To balance the 'for_each_dss_output' loop */
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omapdss_device_put(output);
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break;
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}
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}
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}
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return 0;
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}
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static int omap_compare_pipelines(const void *a, const void *b)
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{
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const struct omap_drm_pipeline *pipe1 = a;
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const struct omap_drm_pipeline *pipe2 = b;
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if (pipe1->alias_id > pipe2->alias_id)
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return 1;
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else if (pipe1->alias_id < pipe2->alias_id)
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return -1;
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return 0;
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}
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static int omap_modeset_init_properties(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
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priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
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num_planes - 1);
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if (!priv->zorder_prop)
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return -ENOMEM;
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return 0;
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}
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static int omap_display_id(struct omap_dss_device *output)
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{
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struct device_node *node = NULL;
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if (output->next) {
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struct omap_dss_device *display;
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display = omapdss_display_get(output);
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node = display->dev->of_node;
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omapdss_device_put(display);
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} else if (output->bridge) {
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struct drm_bridge *bridge = output->bridge;
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while (drm_bridge_get_next_bridge(bridge))
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bridge = drm_bridge_get_next_bridge(bridge);
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node = bridge->of_node;
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} else if (output->panel) {
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node = output->panel->dev->of_node;
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}
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return node ? of_alias_get_id(node, "display") : -ENODEV;
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}
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static int omap_modeset_init(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
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int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
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unsigned int i;
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int ret;
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u32 plane_crtc_mask;
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if (!omapdss_stack_is_ready())
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return -EPROBE_DEFER;
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drm_mode_config_init(dev);
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ret = omap_modeset_init_properties(dev);
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if (ret < 0)
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return ret;
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/*
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* This function creates exactly one connector, encoder, crtc,
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* and primary plane per each connected dss-device. Each
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* connector->encoder->crtc chain is expected to be separate
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* and each crtc is connect to a single dss-channel. If the
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* configuration does not match the expectations or exceeds
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* the available resources, the configuration is rejected.
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*/
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ret = omap_connect_pipelines(dev);
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if (ret < 0)
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return ret;
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if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
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dev_err(dev->dev, "%s(): Too many connected displays\n",
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__func__);
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return -EINVAL;
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}
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/* Create all planes first. They can all be put to any CRTC. */
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plane_crtc_mask = (1 << priv->num_pipes) - 1;
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for (i = 0; i < num_ovls; i++) {
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enum drm_plane_type type = i < priv->num_pipes
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? DRM_PLANE_TYPE_PRIMARY
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: DRM_PLANE_TYPE_OVERLAY;
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struct drm_plane *plane;
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if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
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return -EINVAL;
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plane = omap_plane_init(dev, i, type, plane_crtc_mask);
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if (IS_ERR(plane))
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return PTR_ERR(plane);
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priv->planes[priv->num_planes++] = plane;
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}
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/*
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* Create the encoders, attach the bridges and get the pipeline alias
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* IDs.
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*/
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for (i = 0; i < priv->num_pipes; i++) {
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struct omap_drm_pipeline *pipe = &priv->pipes[i];
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int id;
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pipe->encoder = omap_encoder_init(dev, pipe->output);
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if (!pipe->encoder)
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return -ENOMEM;
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if (pipe->output->bridge) {
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ret = drm_bridge_attach(pipe->encoder,
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pipe->output->bridge, NULL);
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if (ret < 0)
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return ret;
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}
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id = omap_display_id(pipe->output);
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pipe->alias_id = id >= 0 ? id : i;
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}
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/* Sort the pipelines by DT aliases. */
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sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
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omap_compare_pipelines, NULL);
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/*
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* Populate the pipeline lookup table by DISPC channel. Only one display
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* is allowed per channel.
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*/
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for (i = 0; i < priv->num_pipes; ++i) {
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struct omap_drm_pipeline *pipe = &priv->pipes[i];
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enum omap_channel channel = pipe->output->dispc_channel;
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if (WARN_ON(priv->channels[channel] != NULL))
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return -EINVAL;
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priv->channels[channel] = pipe;
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}
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/* Create the connectors and CRTCs. */
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for (i = 0; i < priv->num_pipes; i++) {
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struct omap_drm_pipeline *pipe = &priv->pipes[i];
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struct drm_encoder *encoder = pipe->encoder;
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struct drm_crtc *crtc;
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if (!pipe->output->bridge) {
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pipe->connector = omap_connector_init(dev, pipe->output,
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encoder);
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if (!pipe->connector)
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return -ENOMEM;
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drm_connector_attach_encoder(pipe->connector, encoder);
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if (pipe->output->panel) {
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ret = drm_panel_attach(pipe->output->panel,
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pipe->connector);
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if (ret < 0)
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return ret;
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}
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}
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crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
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if (IS_ERR(crtc))
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return PTR_ERR(crtc);
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encoder->possible_crtcs = 1 << i;
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pipe->crtc = crtc;
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}
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DBG("registered %u planes, %u crtcs/encoders/connectors\n",
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priv->num_planes, priv->num_pipes);
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dev->mode_config.min_width = 8;
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dev->mode_config.min_height = 2;
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/*
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* Note: these values are used for multiple independent things:
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* connector mode filtering, buffer sizes, crtc sizes...
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* Use big enough values here to cover all use cases, and do more
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* specific checking in the respective code paths.
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*/
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dev->mode_config.max_width = 8192;
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dev->mode_config.max_height = 8192;
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/* We want the zpos to be normalized */
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dev->mode_config.normalize_zpos = true;
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dev->mode_config.funcs = &omap_mode_config_funcs;
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dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
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drm_mode_config_reset(dev);
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omap_drm_irq_install(dev);
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return 0;
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}
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/*
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* Enable the HPD in external components if supported
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*/
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static void omap_modeset_enable_external_hpd(struct drm_device *ddev)
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{
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struct omap_drm_private *priv = ddev->dev_private;
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unsigned int i;
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for (i = 0; i < priv->num_pipes; i++) {
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if (priv->pipes[i].connector)
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omap_connector_enable_hpd(priv->pipes[i].connector);
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}
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}
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/*
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* Disable the HPD in external components if supported
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*/
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static void omap_modeset_disable_external_hpd(struct drm_device *ddev)
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{
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struct omap_drm_private *priv = ddev->dev_private;
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unsigned int i;
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for (i = 0; i < priv->num_pipes; i++) {
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if (priv->pipes[i].connector)
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omap_connector_disable_hpd(priv->pipes[i].connector);
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}
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}
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/*
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* drm ioctl funcs
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*/
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static int ioctl_get_param(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct omap_drm_private *priv = dev->dev_private;
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struct drm_omap_param *args = data;
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DBG("%p: param=%llu", dev, args->param);
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switch (args->param) {
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case OMAP_PARAM_CHIPSET_ID:
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args->value = priv->omaprev;
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break;
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default:
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DBG("unknown parameter %lld", args->param);
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return -EINVAL;
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}
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return 0;
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}
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#define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
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static int ioctl_gem_new(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_omap_gem_new *args = data;
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u32 flags = args->flags & OMAP_BO_USER_MASK;
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VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
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args->size.bytes, flags);
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return omap_gem_new_handle(dev, file_priv, args->size, flags,
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&args->handle);
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}
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static int ioctl_gem_info(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_omap_gem_info *args = data;
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struct drm_gem_object *obj;
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int ret = 0;
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VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
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obj = drm_gem_object_lookup(file_priv, args->handle);
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if (!obj)
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return -ENOENT;
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args->size = omap_gem_mmap_size(obj);
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args->offset = omap_gem_mmap_offset(obj);
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drm_gem_object_put_unlocked(obj);
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return ret;
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}
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static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
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DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
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DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
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DRM_RENDER_ALLOW),
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/* Deprecated, to be removed. */
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DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
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DRM_RENDER_ALLOW),
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/* Deprecated, to be removed. */
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DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
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DRM_RENDER_ALLOW),
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};
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/*
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* drm driver funcs
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*/
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static int dev_open(struct drm_device *dev, struct drm_file *file)
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{
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file->driver_priv = NULL;
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DBG("open: dev=%p, file=%p", dev, file);
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return 0;
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}
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static const struct vm_operations_struct omap_gem_vm_ops = {
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.fault = omap_gem_fault,
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.open = drm_gem_vm_open,
|
|
.close = drm_gem_vm_close,
|
|
};
|
|
|
|
static const struct file_operations omapdriver_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.unlocked_ioctl = drm_ioctl,
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
.release = drm_release,
|
|
.mmap = omap_gem_mmap,
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
.llseek = noop_llseek,
|
|
};
|
|
|
|
static struct drm_driver omap_drm_driver = {
|
|
.driver_features = DRIVER_MODESET | DRIVER_GEM |
|
|
DRIVER_ATOMIC | DRIVER_RENDER,
|
|
.open = dev_open,
|
|
.lastclose = drm_fb_helper_lastclose,
|
|
#ifdef CONFIG_DEBUG_FS
|
|
.debugfs_init = omap_debugfs_init,
|
|
#endif
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_export = omap_gem_prime_export,
|
|
.gem_prime_import = omap_gem_prime_import,
|
|
.gem_free_object_unlocked = omap_gem_free_object,
|
|
.gem_vm_ops = &omap_gem_vm_ops,
|
|
.dumb_create = omap_gem_dumb_create,
|
|
.dumb_map_offset = omap_gem_dumb_map_offset,
|
|
.ioctls = ioctls,
|
|
.num_ioctls = DRM_OMAP_NUM_IOCTLS,
|
|
.fops = &omapdriver_fops,
|
|
.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = DRIVER_MAJOR,
|
|
.minor = DRIVER_MINOR,
|
|
.patchlevel = DRIVER_PATCHLEVEL,
|
|
};
|
|
|
|
static const struct soc_device_attribute omapdrm_soc_devices[] = {
|
|
{ .family = "OMAP3", .data = (void *)0x3430 },
|
|
{ .family = "OMAP4", .data = (void *)0x4430 },
|
|
{ .family = "OMAP5", .data = (void *)0x5430 },
|
|
{ .family = "DRA7", .data = (void *)0x0752 },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
|
|
{
|
|
const struct soc_device_attribute *soc;
|
|
struct drm_device *ddev;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
DBG("%s", dev_name(dev));
|
|
|
|
/* Allocate and initialize the DRM device. */
|
|
ddev = drm_dev_alloc(&omap_drm_driver, dev);
|
|
if (IS_ERR(ddev))
|
|
return PTR_ERR(ddev);
|
|
|
|
priv->ddev = ddev;
|
|
ddev->dev_private = priv;
|
|
|
|
priv->dev = dev;
|
|
priv->dss = omapdss_get_dss();
|
|
priv->dispc = dispc_get_dispc(priv->dss);
|
|
priv->dispc_ops = dispc_get_ops(priv->dss);
|
|
|
|
omap_crtc_pre_init(priv);
|
|
|
|
soc = soc_device_match(omapdrm_soc_devices);
|
|
priv->omaprev = soc ? (unsigned int)soc->data : 0;
|
|
priv->wq = alloc_ordered_workqueue("omapdrm", 0);
|
|
|
|
mutex_init(&priv->list_lock);
|
|
INIT_LIST_HEAD(&priv->obj_list);
|
|
|
|
/* Get memory bandwidth limits */
|
|
if (priv->dispc_ops->get_memory_bandwidth_limit)
|
|
priv->max_bandwidth =
|
|
priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
|
|
|
|
omap_gem_init(ddev);
|
|
|
|
ret = omap_modeset_init(ddev);
|
|
if (ret) {
|
|
dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
|
|
goto err_gem_deinit;
|
|
}
|
|
|
|
/* Initialize vblank handling, start with all CRTCs disabled. */
|
|
ret = drm_vblank_init(ddev, priv->num_pipes);
|
|
if (ret) {
|
|
dev_err(priv->dev, "could not init vblank\n");
|
|
goto err_cleanup_modeset;
|
|
}
|
|
|
|
for (i = 0; i < priv->num_pipes; i++)
|
|
drm_crtc_vblank_off(priv->pipes[i].crtc);
|
|
|
|
omap_fbdev_init(ddev);
|
|
|
|
drm_kms_helper_poll_init(ddev);
|
|
omap_modeset_enable_external_hpd(ddev);
|
|
|
|
/*
|
|
* Register the DRM device with the core and the connectors with
|
|
* sysfs.
|
|
*/
|
|
ret = drm_dev_register(ddev, 0);
|
|
if (ret)
|
|
goto err_cleanup_helpers;
|
|
|
|
return 0;
|
|
|
|
err_cleanup_helpers:
|
|
omap_modeset_disable_external_hpd(ddev);
|
|
drm_kms_helper_poll_fini(ddev);
|
|
|
|
omap_fbdev_fini(ddev);
|
|
err_cleanup_modeset:
|
|
drm_mode_config_cleanup(ddev);
|
|
omap_drm_irq_uninstall(ddev);
|
|
err_gem_deinit:
|
|
omap_gem_deinit(ddev);
|
|
destroy_workqueue(priv->wq);
|
|
omap_disconnect_pipelines(ddev);
|
|
omap_crtc_pre_uninit(priv);
|
|
drm_dev_put(ddev);
|
|
return ret;
|
|
}
|
|
|
|
static void omapdrm_cleanup(struct omap_drm_private *priv)
|
|
{
|
|
struct drm_device *ddev = priv->ddev;
|
|
|
|
DBG("");
|
|
|
|
drm_dev_unregister(ddev);
|
|
|
|
omap_modeset_disable_external_hpd(ddev);
|
|
drm_kms_helper_poll_fini(ddev);
|
|
|
|
omap_fbdev_fini(ddev);
|
|
|
|
drm_atomic_helper_shutdown(ddev);
|
|
|
|
drm_mode_config_cleanup(ddev);
|
|
|
|
omap_drm_irq_uninstall(ddev);
|
|
omap_gem_deinit(ddev);
|
|
|
|
destroy_workqueue(priv->wq);
|
|
|
|
omap_disconnect_pipelines(ddev);
|
|
omap_crtc_pre_uninit(priv);
|
|
|
|
drm_dev_put(ddev);
|
|
}
|
|
|
|
static int pdev_probe(struct platform_device *pdev)
|
|
{
|
|
struct omap_drm_private *priv;
|
|
int ret;
|
|
|
|
if (omapdss_is_initialized() == false)
|
|
return -EPROBE_DEFER;
|
|
|
|
ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to set the DMA mask\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Allocate and initialize the driver private structure. */
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = omapdrm_init(priv, &pdev->dev);
|
|
if (ret < 0)
|
|
kfree(priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pdev_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_drm_private *priv = platform_get_drvdata(pdev);
|
|
|
|
omapdrm_cleanup(priv);
|
|
kfree(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int omap_drm_suspend(struct device *dev)
|
|
{
|
|
struct omap_drm_private *priv = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = priv->ddev;
|
|
|
|
return drm_mode_config_helper_suspend(drm_dev);
|
|
}
|
|
|
|
static int omap_drm_resume(struct device *dev)
|
|
{
|
|
struct omap_drm_private *priv = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = priv->ddev;
|
|
|
|
drm_mode_config_helper_resume(drm_dev);
|
|
|
|
return omap_gem_resume(drm_dev);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
|
|
|
|
static struct platform_driver pdev = {
|
|
.driver = {
|
|
.name = "omapdrm",
|
|
.pm = &omapdrm_pm_ops,
|
|
},
|
|
.probe = pdev_probe,
|
|
.remove = pdev_remove,
|
|
};
|
|
|
|
static struct platform_driver * const drivers[] = {
|
|
&omap_dmm_driver,
|
|
&pdev,
|
|
};
|
|
|
|
static int __init omap_drm_init(void)
|
|
{
|
|
DBG("init");
|
|
|
|
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
|
}
|
|
|
|
static void __exit omap_drm_fini(void)
|
|
{
|
|
DBG("fini");
|
|
|
|
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
|
}
|
|
|
|
/* need late_initcall() so we load after dss_driver's are loaded */
|
|
late_initcall(omap_drm_init);
|
|
module_exit(omap_drm_fini);
|
|
|
|
MODULE_AUTHOR("Rob Clark <rob@ti.com>");
|
|
MODULE_DESCRIPTION("OMAP DRM Display Driver");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
MODULE_LICENSE("GPL v2");
|