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a1d2a63399
- Mali 4xx GPUs have two kinds of processors GP and PP. GP is for OpenGL vertex shader processing and PP is for fragment shader processing. Each processor has its own MMU so prcessors work in virtual address space. - There's only one GP but multiple PP (max 4 for mali 400 and 8 for mali 450) in the same mali 4xx GPU. All PPs are grouped togather to handle a single fragment shader task divided by FB output tiled pixels. Mali 400 user space driver is responsible for assign target tiled pixels to each PP, but mali 450 has a HW module called DLBU to dynamically balance each PP's load. - User space driver allocate buffer object and map into GPU virtual address space, upload command stream and draw data with CPU mmap of the buffer object, then submit task to GP/PP with a register frame indicating where is the command stream and misc settings. - There's no command stream validation/relocation due to each user process has its own GPU virtual address space. GP/PP's MMU switch virtual address space before running two tasks from different user process. Error or evil user space code just get MMU fault or GP/PP error IRQ, then the HW/SW will be recovered. - Use GEM+shmem for MM. Currently just alloc and pin memory when gem object creation. GPU vm map of the buffer is also done in the alloc stage in kernel space. We may delay the memory allocation and real GPU vm map to command submission stage in the furture as improvement. - Use drm_sched for GPU task schedule. Each OpenGL context should have a lima context object in the kernel to distinguish tasks from different user. drm_sched gets task from each lima context in a fair way. mesa driver can be found here before upstreamed: https://gitlab.freedesktop.org/lima/mesa v8: - add comments for in_sync - fix ctx free miss mutex unlock v7: - remove lima_fence_ops with default value - move fence slab create to device probe - check pad ioctl args to be zero - add comments for user/kernel interface v6: - fix comments by checkpatch.pl v5: - export gp/pp version to userspace - rebase on drm-misc-next v4: - use get param interface to get info - separate context create/free ioctl - remove unused max sched task param - update copyright time - use xarray instead of idr - stop using drmP.h v3: - fix comments from kbuild robot - restrict supported arch to tested ones v2: - fix syscall argument check - fix job finish fence leak since kernel 5.0 - use drm syncobj to replace native fence - move buffer object GPU va map into kernel - reserve syscall argument space for future info - remove kernel gem modifier - switch TTM back to GEM+shmem MM - use time based io poll - use whole register name - adopt gem reservation obj integration - use drm_timeout_abs_to_jiffies Cc: Eric Anholt <eric@anholt.net> Cc: Rob Herring <robh@kernel.org> Cc: Christian König <ckoenig.leichtzumerken@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Rob Clark <robdclark@gmail.com> Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de> Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Simon Shields <simon@lineageos.org> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Rob Herring <robh@kerrnel.org> Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/291200/
132 lines
2.2 KiB
C
132 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/* Copyright 2018-2019 Qiang Yu <yuq825@gmail.com> */
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#ifndef __LIMA_DEVICE_H__
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#define __LIMA_DEVICE_H__
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#include <drm/drm_device.h>
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#include <linux/delay.h>
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#include "lima_sched.h"
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enum lima_gpu_id {
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lima_gpu_mali400 = 0,
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lima_gpu_mali450,
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lima_gpu_num,
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};
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enum lima_ip_id {
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lima_ip_pmu,
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lima_ip_gpmmu,
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lima_ip_ppmmu0,
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lima_ip_ppmmu1,
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lima_ip_ppmmu2,
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lima_ip_ppmmu3,
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lima_ip_ppmmu4,
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lima_ip_ppmmu5,
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lima_ip_ppmmu6,
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lima_ip_ppmmu7,
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lima_ip_gp,
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lima_ip_pp0,
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lima_ip_pp1,
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lima_ip_pp2,
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lima_ip_pp3,
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lima_ip_pp4,
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lima_ip_pp5,
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lima_ip_pp6,
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lima_ip_pp7,
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lima_ip_l2_cache0,
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lima_ip_l2_cache1,
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lima_ip_l2_cache2,
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lima_ip_dlbu,
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lima_ip_bcast,
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lima_ip_pp_bcast,
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lima_ip_ppmmu_bcast,
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lima_ip_num,
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};
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struct lima_device;
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struct lima_ip {
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struct lima_device *dev;
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enum lima_ip_id id;
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bool present;
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void __iomem *iomem;
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int irq;
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union {
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/* gp/pp */
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bool async_reset;
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/* l2 cache */
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spinlock_t lock;
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} data;
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};
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enum lima_pipe_id {
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lima_pipe_gp,
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lima_pipe_pp,
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lima_pipe_num,
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};
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struct lima_device {
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struct device *dev;
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struct drm_device *ddev;
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struct platform_device *pdev;
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enum lima_gpu_id id;
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u32 gp_version;
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u32 pp_version;
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int num_pp;
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void __iomem *iomem;
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struct clk *clk_bus;
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struct clk *clk_gpu;
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struct reset_control *reset;
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struct regulator *regulator;
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struct lima_ip ip[lima_ip_num];
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struct lima_sched_pipe pipe[lima_pipe_num];
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struct lima_vm *empty_vm;
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uint64_t va_start;
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uint64_t va_end;
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u32 *dlbu_cpu;
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dma_addr_t dlbu_dma;
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};
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static inline struct lima_device *
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to_lima_dev(struct drm_device *dev)
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{
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return dev->dev_private;
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}
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int lima_device_init(struct lima_device *ldev);
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void lima_device_fini(struct lima_device *ldev);
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const char *lima_ip_name(struct lima_ip *ip);
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typedef int (*lima_poll_func_t)(struct lima_ip *);
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static inline int lima_poll_timeout(struct lima_ip *ip, lima_poll_func_t func,
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int sleep_us, int timeout_us)
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{
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ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
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might_sleep_if(sleep_us);
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while (1) {
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if (func(ip))
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return 0;
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if (timeout_us && ktime_compare(ktime_get(), timeout) > 0)
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return -ETIMEDOUT;
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if (sleep_us)
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usleep_range((sleep_us >> 2) + 1, sleep_us);
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}
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return 0;
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}
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#endif
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