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3bb72d86d8
CPACR_EL1 has several bitfields for controlling traps for floating point features to EL1, each of which has a separate bits for EL0 and EL1. Marc Zyngier noted that we are not consistent in our use of defines to manipulate these, sometimes using a define covering the whole field and sometimes using defines for the individual bits. Make this consistent by expanding the whole field defines where they are used (currently only in the KVM code) and deleting them so that no further uses can be introduced. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220207152109.197566-3-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
363 lines
12 KiB
C
363 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM64_KVM_ARM_H__
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#define __ARM64_KVM_ARM_H__
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#include <asm/esr.h>
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#include <asm/memory.h>
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#include <asm/types.h>
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/* Hyp Configuration Register (HCR) bits */
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#define HCR_TID5 (UL(1) << 58)
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#define HCR_DCT (UL(1) << 57)
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#define HCR_ATA_SHIFT 56
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#define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
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#define HCR_AMVOFFEN (UL(1) << 51)
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#define HCR_FIEN (UL(1) << 47)
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#define HCR_FWB (UL(1) << 46)
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#define HCR_API (UL(1) << 41)
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#define HCR_APK (UL(1) << 40)
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#define HCR_TEA (UL(1) << 37)
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#define HCR_TERR (UL(1) << 36)
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#define HCR_TLOR (UL(1) << 35)
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#define HCR_E2H (UL(1) << 34)
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#define HCR_ID (UL(1) << 33)
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#define HCR_CD (UL(1) << 32)
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#define HCR_RW_SHIFT 31
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#define HCR_RW (UL(1) << HCR_RW_SHIFT)
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#define HCR_TRVM (UL(1) << 30)
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#define HCR_HCD (UL(1) << 29)
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#define HCR_TDZ (UL(1) << 28)
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#define HCR_TGE (UL(1) << 27)
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#define HCR_TVM (UL(1) << 26)
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#define HCR_TTLB (UL(1) << 25)
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#define HCR_TPU (UL(1) << 24)
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#define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
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#define HCR_TSW (UL(1) << 22)
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#define HCR_TACR (UL(1) << 21)
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#define HCR_TIDCP (UL(1) << 20)
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#define HCR_TSC (UL(1) << 19)
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#define HCR_TID3 (UL(1) << 18)
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#define HCR_TID2 (UL(1) << 17)
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#define HCR_TID1 (UL(1) << 16)
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#define HCR_TID0 (UL(1) << 15)
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#define HCR_TWE (UL(1) << 14)
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#define HCR_TWI (UL(1) << 13)
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#define HCR_DC (UL(1) << 12)
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#define HCR_BSU (3 << 10)
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#define HCR_BSU_IS (UL(1) << 10)
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#define HCR_FB (UL(1) << 9)
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#define HCR_VSE (UL(1) << 8)
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#define HCR_VI (UL(1) << 7)
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#define HCR_VF (UL(1) << 6)
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#define HCR_AMO (UL(1) << 5)
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#define HCR_IMO (UL(1) << 4)
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#define HCR_FMO (UL(1) << 3)
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#define HCR_PTW (UL(1) << 2)
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#define HCR_SWIO (UL(1) << 1)
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#define HCR_VM (UL(1) << 0)
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#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39))
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/*
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* The bits we set in HCR:
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* TLOR: Trap LORegion register accesses
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* RW: 64bit by default, can be overridden for 32bit VMs
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* TACR: Trap ACTLR
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* TSC: Trap SMC
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* TSW: Trap cache operations by set/way
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* TWE: Trap WFE
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* TWI: Trap WFI
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* TIDCP: Trap L2CTLR/L2ECTLR
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* BSU_IS: Upgrade barriers to the inner shareable domain
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* FB: Force broadcast of all maintenance operations
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* AMO: Override CPSR.A and enable signaling with VA
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* IMO: Override CPSR.I and enable signaling with VI
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* FMO: Override CPSR.F and enable signaling with VF
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* SWIO: Turn set/way invalidates into set/way clean+invalidate
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* PTW: Take a stage2 fault if a stage1 walk steps in device memory
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*/
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#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
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HCR_BSU_IS | HCR_FB | HCR_TACR | \
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HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
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HCR_FMO | HCR_IMO | HCR_PTW )
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#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
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#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
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#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
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#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
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/* TCR_EL2 Registers bits */
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#define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
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#define TCR_EL2_TBI (1 << 20)
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#define TCR_EL2_PS_SHIFT 16
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#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_TG0_MASK TCR_TG0_MASK
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#define TCR_EL2_SH0_MASK TCR_SH0_MASK
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#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
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#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
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#define TCR_EL2_T0SZ_MASK 0x3f
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#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
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TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
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/* VTCR_EL2 Registers bits */
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#define VTCR_EL2_RES1 (1U << 31)
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#define VTCR_EL2_HD (1 << 22)
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#define VTCR_EL2_HA (1 << 21)
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#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
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#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
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#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
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#define VTCR_EL2_TG0_4K TCR_TG0_4K
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#define VTCR_EL2_TG0_16K TCR_TG0_16K
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#define VTCR_EL2_TG0_64K TCR_TG0_64K
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#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
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#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
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#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
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#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
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#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
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#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
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#define VTCR_EL2_SL0_SHIFT 6
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#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_T0SZ_MASK 0x3f
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#define VTCR_EL2_VS_SHIFT 19
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#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
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#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
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#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
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/*
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* We configure the Stage-2 page tables to always restrict the IPA space to be
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* 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
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* not known to exist and will break with this configuration.
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*
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* The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
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*
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* Note that when using 4K pages, we concatenate two first level page tables
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* together. With 16K pages, we concatenate 16 first level page tables.
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*
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*/
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#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
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VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
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/*
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* VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
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* Interestingly, it depends on the page size.
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* See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
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*
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* -----------------------------------------
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* | Entry level | 4K | 16K/64K |
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* ------------------------------------------
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* | Level: 0 | 2 | - |
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* ------------------------------------------
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* | Level: 1 | 1 | 2 |
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* ------------------------------------------
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* | Level: 2 | 0 | 1 |
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* ------------------------------------------
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* | Level: 3 | - | 0 |
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* ------------------------------------------
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*
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* The table roughly translates to :
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*
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* SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
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*
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* Where TGRAN_SL0_BASE is a magic number depending on the page size:
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* TGRAN_SL0_BASE(4K) = 2
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* TGRAN_SL0_BASE(16K) = 3
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* TGRAN_SL0_BASE(64K) = 3
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* provided we take care of ruling out the unsupported cases and
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* Entry_Level = 4 - Number_of_levels.
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*
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*/
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#ifdef CONFIG_ARM64_64K_PAGES
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#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
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#define VTCR_EL2_TGRAN_SL0_BASE 3UL
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
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#define VTCR_EL2_TGRAN_SL0_BASE 3UL
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#else /* 4K */
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#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
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#define VTCR_EL2_TGRAN_SL0_BASE 2UL
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#endif
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#define VTCR_EL2_LVLS_TO_SL0(levels) \
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((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_SL0_TO_LVLS(sl0) \
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((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
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#define VTCR_EL2_LVLS(vtcr) \
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VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
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#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
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/*
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* ARM VMSAv8-64 defines an algorithm for finding the translation table
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* descriptors in section D4.2.8 in ARM DDI 0487C.a.
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*
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* The algorithm defines the expectations on the translation table
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* addresses for each level, based on PAGE_SIZE, entry level
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* and the translation table size (T0SZ). The variable "x" in the
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* algorithm determines the alignment of a table base address at a given
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* level and thus determines the alignment of VTTBR:BADDR for stage2
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* page table entry level.
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* Since the number of bits resolved at the entry level could vary
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* depending on the T0SZ, the value of "x" is defined based on a
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* Magic constant for a given PAGE_SIZE and Entry Level. The
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* intermediate levels must be always aligned to the PAGE_SIZE (i.e,
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* x = PAGE_SHIFT).
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*
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* The value of "x" for entry level is calculated as :
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* x = Magic_N - T0SZ
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*
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* where Magic_N is an integer depending on the page size and the entry
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* level of the page table as below:
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*
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* --------------------------------------------
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* | Entry level | 4K 16K 64K |
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* --------------------------------------------
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* | Level: 0 (4 levels) | 28 | - | - |
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* --------------------------------------------
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* | Level: 1 (3 levels) | 37 | 31 | 25 |
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* --------------------------------------------
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* | Level: 2 (2 levels) | 46 | 42 | 38 |
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* --------------------------------------------
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* | Level: 3 (1 level) | - | 53 | 51 |
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* --------------------------------------------
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*
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* We have a magic formula for the Magic_N below:
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*
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* Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
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*
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* where Number_of_levels = (4 - Level). We are only interested in the
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* value for Entry_Level for the stage2 page table.
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*
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* So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
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*
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* x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
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* = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
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*
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* Here is one way to explain the Magic Formula:
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*
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* x = log2(Size_of_Entry_Level_Table)
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*
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* Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
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* PAGE_SHIFT bits in the PTE, we have :
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*
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* Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
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* = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
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* where n = number of levels, and since each pointer is 8bytes, we have:
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*
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* x = Bits_Entry_Level + 3
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* = IPA_SHIFT - (PAGE_SHIFT - 3) * n
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*
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* The only constraint here is that, we have to find the number of page table
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* levels for a given IPA size (which we do, see stage2_pt_levels())
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*/
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#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
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#define VTTBR_CNP_BIT (UL(1))
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#define VTTBR_VMID_SHIFT (UL(48))
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#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
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/* Hyp System Trap Register */
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#define HSTR_EL2_T(x) (1 << x)
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/* Hyp Coprocessor Trap Register Shifts */
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#define CPTR_EL2_TFP_SHIFT 10
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/* Hyp Coprocessor Trap Register */
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#define CPTR_EL2_TCPAC (1U << 31)
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#define CPTR_EL2_TAM (1 << 30)
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#define CPTR_EL2_TTA (1 << 20)
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#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
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#define CPTR_EL2_TZ (1 << 8)
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#define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
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#define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1
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#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \
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GENMASK(29, 21) | \
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GENMASK(19, 14) | \
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BIT(11))
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/* Hyp Debug Configuration Register bits */
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#define MDCR_EL2_E2TB_MASK (UL(0x3))
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#define MDCR_EL2_E2TB_SHIFT (UL(24))
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#define MDCR_EL2_HPMFZS (UL(1) << 36)
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#define MDCR_EL2_HPMFZO (UL(1) << 29)
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#define MDCR_EL2_MTPME (UL(1) << 28)
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#define MDCR_EL2_TDCC (UL(1) << 27)
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#define MDCR_EL2_HLP (UL(1) << 26)
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#define MDCR_EL2_HCCD (UL(1) << 23)
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#define MDCR_EL2_TTRF (UL(1) << 19)
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#define MDCR_EL2_HPMD (UL(1) << 17)
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#define MDCR_EL2_TPMS (UL(1) << 14)
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#define MDCR_EL2_E2PB_MASK (UL(0x3))
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#define MDCR_EL2_E2PB_SHIFT (UL(12))
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#define MDCR_EL2_TDRA (UL(1) << 11)
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#define MDCR_EL2_TDOSA (UL(1) << 10)
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#define MDCR_EL2_TDA (UL(1) << 9)
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#define MDCR_EL2_TDE (UL(1) << 8)
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#define MDCR_EL2_HPME (UL(1) << 7)
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#define MDCR_EL2_TPM (UL(1) << 6)
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#define MDCR_EL2_TPMCR (UL(1) << 5)
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#define MDCR_EL2_HPMN_MASK (UL(0x1F))
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#define MDCR_EL2_RES0 (GENMASK(63, 37) | \
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GENMASK(35, 30) | \
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GENMASK(25, 24) | \
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GENMASK(22, 20) | \
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BIT(18) | \
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GENMASK(16, 15))
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/* For compatibility with fault code shared with 32-bit */
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#define FSC_FAULT ESR_ELx_FSC_FAULT
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#define FSC_ACCESS ESR_ELx_FSC_ACCESS
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#define FSC_PERM ESR_ELx_FSC_PERM
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#define FSC_SEA ESR_ELx_FSC_EXTABT
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#define FSC_SEA_TTW0 (0x14)
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#define FSC_SEA_TTW1 (0x15)
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#define FSC_SEA_TTW2 (0x16)
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#define FSC_SEA_TTW3 (0x17)
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#define FSC_SECC (0x18)
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#define FSC_SECC_TTW0 (0x1c)
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#define FSC_SECC_TTW1 (0x1d)
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#define FSC_SECC_TTW2 (0x1e)
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#define FSC_SECC_TTW3 (0x1f)
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/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
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#define HPFAR_MASK (~UL(0xf))
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/*
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* We have
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* PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
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* HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
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*/
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#define PAR_TO_HPFAR(par) \
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(((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
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#define ECN(x) { ESR_ELx_EC_##x, #x }
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#define kvm_arm_exception_class \
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ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
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ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
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ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
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ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
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ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
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ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
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ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
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ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
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ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
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#define CPACR_EL1_TTA (1 << 28)
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#define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |\
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CPACR_EL1_ZEN_EL1EN)
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#endif /* __ARM64_KVM_ARM_H__ */
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