mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-24 19:45:06 +08:00
6ad63dec9c
This is a smaller update than the past few times, but with just over
500 non-merge changesets still dwarfes the rest of the SoC tree.
Three new SoC platforms get added, each one a follow-up to an existing
product, and added here in combination with a reference platform:
- Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html
- Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for
Rich Graphics Applications".
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html
- NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
These are actual commercial products we now support with an in-kernel
device tree source file:
- Bosch Guardian is a product made by Bosch Power
Tools GmbH, based on the Texas Instruments AM335x chip
- Winterland IceBoard is a Texas Instruments AM3874 based
machine used in telescopes at the south pole and elsewhere, see commit
d031773169 for some pointers:
- Inspur on5263m5 is an x86 server platform with an Aspeed
ast2500 baseboard management controller. This is for running on
the BMC.
- Zodiac Digital Tapping Unit, apparently a kind of ethernet
switch used in airplanes.
- Phicomm K3 is a WiFi router based on Broadcom bcm47094
- Methode Electronics uDPU FTTdp distribution point unit
- X96 Max, a generic TV box based on Amlogic G12a (S905X2)
- NVIDIA Shield TV (Darcy) based on Tegra210
And then there are several new SBC, evaluation, development or modular
systems that we add:
- Three new Rockchips rk3399 based boards:
- FriendlyElec NanoPC-T4 and NanoPi M4
- Radxa ROCK Pi 4
- Five new i.MX6 family SoM modules and boards for industrial
products:
- Logic PD i.MX6QD SoM and evaluation baseboad
- Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
- Phytec phyCORE i.MX6 UltraLite SoM and evaluation module
- MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
microcontroller
- Chameleon96, an Intel/Altera Cyclone5 based FPGA development
system in 96boards form factor
- Arm Fixed Virtual Platforms(FVP) Base RevC, a purely
virtual platform for corresponding to the latest "fast model"
- Another Raspberry Pi variant: Model 3 A+, supported both
in 32-bit and 64-bit mode.
- Oxalis Evalkit V100 based on NXP Layerscape LS1012a,
in 96Boards enterprise form factor
- Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108
For already supported boards and SoCs, we often add support for new
devices after merging the drivers. This time, the largest changes include
updates for
- STMicroelectronics stm32mp1, which was now formally
launched last week
- Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip
- Action Semi S700
- TI AM654x, their recently merged 64-bit SoC from the OMAP family
- Various Amlogic Meson SoCs
- Mediatek MT2712
- NVIDIA Tegra186 and Tegra210
- The ancient NXP lpc32xx family
- Samsung s5pv210, used in some older mobile phones
Many other chips see smaller updates and bugfixes beyond that.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJcf9c1AAoJEGCrR//JCVInvl8QAIgmK09QZr3VAD5WnKSoWwiX
GP1+qgmr/cbIF9X+Kt/0Y2E+oIi9uxu7v5iwpYf0inzV4QOKwy9LvpeInd7s07bf
hSPMN0wZ9bV5Ylk0YtlvGvOQTqys9oweeSEkHfjQ8Jm7aFkaRXQ1dt23d8KLILoB
8GKk9A4ncn1AB1vu6xBqeqBiaQiqhMjb9paWkmjYrjhP22hHlVyGlMd8cwfG+A5a
5Ft4lWkzvgrXPMwZgrCGU233OV5UHrn2A8ohiIUN5J6aSWxu8eMEryU+MF0poidl
malJ+AHl2mK83YN3wYemxy/lEJzAW4PrjCVgY2bRDqwlOnI3+d+z7rVSfuMCzSKs
TDTbv9VqPJhsZFr/GIkvB3iwnYfvP/mXrzM7gbw7rQqthEKOy+3HtZwmHAKF4QNK
TT4wyngC/CwiyULEwtPCjbxZ/7yal6sygllioCo+M2OHeattIQEnqi/Yvc0vx/th
th9Pepf26jUp/ZJNlxk0XDyBMPhUf6sHUvh7a+y6l6ZxZ6avbFdGPeJrQe5HF2Sp
KM7BH3w/CpoNRSKs37mR7JpNdYNDSonItgaIm5xVJZk+Wr/BWgtcr6BbGD/vlT7N
kIDDinyhczhvhpTmWs6QZdZNQmf6bASzTVeFv2+ES+kXt/AKhv0O5N4Pw/oU+VBv
pD5+7YjjA0fMKcYae3gs
=1goV
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC device tree updates from Arnd Bergmann:
"This is a smaller update than the past few times, but with just over
500 non-merge changesets still dwarfes the rest of the SoC tree.
Three new SoC platforms get added, each one a follow-up to an existing
product, and added here in combination with a reference platform:
- Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging
processor:
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html
- Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics
Applications":
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html
- NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC:
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
These are actual commercial products we now support with an in-kernel
device tree source file:
- Bosch Guardian is a product made by Bosch Power Tools GmbH, based
on the Texas Instruments AM335x chip
- Winterland IceBoard is a Texas Instruments AM3874 based machine
used in telescopes at the south pole and elsewhere, see commit
d031773169 for some pointers:
- Inspur on5263m5 is an x86 server platform with an Aspeed ast2500
baseboard management controller. This is for running on the BMC.
- Zodiac Digital Tapping Unit, apparently a kind of ethernet switch
used in airplanes.
- Phicomm K3 is a WiFi router based on Broadcom bcm47094
- Methode Electronics uDPU FTTdp distribution point unit
- X96 Max, a generic TV box based on Amlogic G12a (S905X2)
- NVIDIA Shield TV (Darcy) based on Tegra210
And then there are several new SBC, evaluation, development or modular
systems that we add:
- Three new Rockchips rk3399 based boards:
- FriendlyElec NanoPC-T4 and NanoPi M4
- Radxa ROCK Pi 4
- Five new i.MX6 family SoM modules and boards for industrial
products:
- Logic PD i.MX6QD SoM and evaluation baseboad
- Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
- Phytec phyCORE i.MX6 UltraLite SoM and evaluation module
- MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
microcontroller
- Chameleon96, an Intel/Altera Cyclone5 based FPGA development system
in 96boards form factor
- Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual
platform for corresponding to the latest "fast model"
- Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit
and 64-bit mode.
- Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards
enterprise form factor
- Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108
For already supported boards and SoCs, we often add support for new
devices after merging the drivers. This time, the largest changes
include updates for
- STMicroelectronics stm32mp1, which was now formally launched last
week
- Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip
- Action Semi S700
- TI AM654x, their recently merged 64-bit SoC from the OMAP family
- Various Amlogic Meson SoCs
- Mediatek MT2712
- NVIDIA Tegra186 and Tegra210
- The ancient NXP lpc32xx family
- Samsung s5pv210, used in some older mobile phones
Many other chips see smaller updates and bugfixes beyond that"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits)
ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4
dt-bindings: net: ti: deprecate cpsw-phy-sel bindings
ARM: dts: am335x: switch to use phy-gmii-sel
ARM: dts: am4372: switch to use phy-gmii-sel
ARM: dts: dm814x: switch to use phy-gmii-sel
ARM: dts: dra7: switch to use phy-gmii-sel
arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference
ARM: dts: exynos: Add support for secondary DAI to Odroid XU4
ARM: dts: exynos: Add support for secondary DAI to Odroid XU3
ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite
ARM: dts: exynos: Add stdout path property to Arndale board
ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU
ARM: dts: exynos: Enable ADC on Odroid HC1
arm64: dts: sprd: Remove wildcard compatible string
arm64: dts: sprd: Add SC27XX fuel gauge device
arm64: dts: sprd: Add SC2731 charger device
arm64: dts: sprd: Add ADC calibration support
arm64: dts: sprd: Remove PMIC INTC irq trigger type
arm64: dts: rockchip: Enable tsadc device on rock960
ARM: dts: rockchip: add chosen node on veyron devices
...
534 lines
11 KiB
Plaintext
534 lines
11 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2018
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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/dts-v1/;
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#include "vf610.dtsi"
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/ {
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model = "Liebherr BK4 controller";
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compatible = "lwn,bk4", "fsl,vf610";
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chosen {
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stdout-path = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x8000000>;
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};
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audio_ext: oscillator-audio {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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enet_ext: oscillator-ethernet {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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/* LED D5 */
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led0: heartbeat {
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label = "heartbeat";
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gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_mcu";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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spi-gpio {
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compatible = "spi-gpio";
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pinctrl-0 = <&pinctrl_gpio_spi>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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/* PTD12 ->RPIO[91] */
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sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
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/* PTD10 ->RPIO[89] */
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miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
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num-chipselects = <0>;
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gpio@0 {
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compatible = "pisosr-gpio";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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/* PTB18 -> RGPIO[40] */
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load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <100000>;
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};
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};
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};
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&adc0 {
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&adc1 {
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&can0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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&clks {
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clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
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clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
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};
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&dspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi0>;
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bus-num = <0>;
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status = "okay";
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spidev0@0 {
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compatible = "lwn,bk4";
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spi-max-frequency = <30000000>;
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reg = <0>;
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fsl,spi-cs-sck-delay = <200>;
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fsl,spi-sck-cs-delay = <400>;
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};
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};
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&dspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi3>;
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bus-num = <3>;
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status = "okay";
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spi-slave;
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#address-cells = <0>;
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slave {
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compatible = "lwn,bk4";
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spi-max-frequency = <30000000>;
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};
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};
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&edma0 {
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status = "okay";
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};
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&edma1 {
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&fec0 {
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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reg = <1>;
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clocks = <&clks VF610_CLK_ENET_50M>;
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clock-names = "rmii-ref";
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};
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};
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};
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&fec1 {
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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clocks = <&clks VF610_CLK_ENET_50M>;
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clock-names = "rmii-ref";
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};
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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at24c256: eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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};
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m41t62: rtc@68 {
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compatible = "st,m41t62";
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reg = <0x68>;
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};
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};
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&nfc {
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assigned-clocks = <&clks VF610_CLK_NFC>;
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assigned-clock-rates = <33000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nfc>;
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status = "okay";
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nand@0 {
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compatible = "fsl,vf610-nfc-nandcs";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-bus-width = <16>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <24>;
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nand-ecc-step-size = <2048>;
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nand-on-flash-bbt;
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};
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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status = "okay";
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n25q128a13_4: flash@0 {
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compatible = "n25q128a13", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <66000000>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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};
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n25q128a13_2: flash@1 {
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compatible = "n25q128a13", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <66000000>;
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spi-rx-bus-width = <2>;
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reg = <1>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usbdev0 {
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disable-over-current;
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status = "okay";
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};
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&usbh1 {
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disable-over-current;
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status = "okay";
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};
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&usbmisc0 {
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status = "okay";
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};
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&usbmisc1 {
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status = "okay";
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};
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&usbphy0 {
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status = "okay";
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};
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&usbphy1 {
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* One_Wire_PSU_EN */
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VF610_PAD_PTC29__GPIO_102 0x1183
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/* SPI ENABLE */
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VF610_PAD_PTB26__GPIO_96 0x1183
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/* EB control */
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VF610_PAD_PTE14__GPIO_119 0x1183
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VF610_PAD_PTE4__GPIO_109 0x1181
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/* Feedback_Lines */
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VF610_PAD_PTC31__GPIO_104 0x1181
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VF610_PAD_PTA7__GPIO_134 0x1181
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VF610_PAD_PTD9__GPIO_88 0x1181
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VF610_PAD_PTE1__GPIO_106 0x1183
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VF610_PAD_PTB2__GPIO_24 0x1181
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VF610_PAD_PTB3__GPIO_25 0x1181
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VF610_PAD_PTB1__GPIO_23 0x1181
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/* SDHC Enable */
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VF610_PAD_PTE19__GPIO_124 0x1183
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/* SDHC Overcurrent */
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VF610_PAD_PTB23__GPIO_93 0x1181
|
|
/* GPI */
|
|
VF610_PAD_PTE2__GPIO_107 0x1181
|
|
VF610_PAD_PTE3__GPIO_108 0x1181
|
|
VF610_PAD_PTE5__GPIO_110 0x1181
|
|
VF610_PAD_PTE6__GPIO_111 0x1181
|
|
/* GPO */
|
|
VF610_PAD_PTE0__GPIO_105 0x1183
|
|
VF610_PAD_PTE7__GPIO_112 0x1183
|
|
/* RS485 Control */
|
|
VF610_PAD_PTB8__GPIO_30 0x1183
|
|
VF610_PAD_PTB9__GPIO_31 0x1183
|
|
VF610_PAD_PTE8__GPIO_113 0x1183
|
|
/* MPBUS MPB_EN */
|
|
VF610_PAD_PTE28__GPIO_133 0x1183
|
|
/* MISC */
|
|
VF610_PAD_PTE10__GPIO_115 0x1183
|
|
VF610_PAD_PTE11__GPIO_116 0x1183
|
|
VF610_PAD_PTE17__GPIO_122 0x1183
|
|
VF610_PAD_PTC30__GPIO_103 0x1183
|
|
VF610_PAD_PTB0__GPIO_22 0x1181
|
|
/* RESETINFO */
|
|
VF610_PAD_PTE26__GPIO_131 0x1183
|
|
VF610_PAD_PTD6__GPIO_85 0x1181
|
|
VF610_PAD_PTE27__GPIO_132 0x1181
|
|
VF610_PAD_PTE13__GPIO_118 0x1181
|
|
VF610_PAD_PTE21__GPIO_126 0x1181
|
|
VF610_PAD_PTE22__GPIO_127 0x1181
|
|
/* EE_5V_EN */
|
|
VF610_PAD_PTE18__GPIO_123 0x1183
|
|
/* EE_5V_OC_N */
|
|
VF610_PAD_PTE25__GPIO_130 0x1181
|
|
>;
|
|
};
|
|
|
|
pinctrl_can0: can0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB14__CAN0_RX 0x1181
|
|
VF610_PAD_PTB15__CAN0_TX 0x1182
|
|
>;
|
|
};
|
|
|
|
pinctrl_can1: can1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB16__CAN1_RX 0x1181
|
|
VF610_PAD_PTB17__CAN1_TX 0x1182
|
|
>;
|
|
};
|
|
|
|
pinctrl_dspi0: dspi0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB18__DSPI0_CS1 0x1182
|
|
VF610_PAD_PTB19__DSPI0_CS0 0x1182
|
|
VF610_PAD_PTB20__DSPI0_SIN 0x1181
|
|
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
|
|
VF610_PAD_PTB22__DSPI0_SCK 0x1182
|
|
>;
|
|
};
|
|
|
|
pinctrl_dspi3: dspi3grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD10__DSPI3_CS0 0x1181
|
|
VF610_PAD_PTD11__DSPI3_SIN 0x1181
|
|
VF610_PAD_PTD12__DSPI3_SOUT 0x1182
|
|
VF610_PAD_PTD13__DSPI3_SCK 0x1181
|
|
>;
|
|
};
|
|
|
|
pinctrl_esdhc1: esdhc1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
|
|
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
|
|
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
|
|
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
|
|
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
|
|
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
|
|
VF610_PAD_PTB28__GPIO_98 0x219d
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec0: fec0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA6__RMII_CLKIN 0x30dd
|
|
VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de
|
|
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
|
|
VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd
|
|
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
|
|
VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
|
|
VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
|
|
VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
|
|
VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
|
|
VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec1: fec1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de
|
|
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df
|
|
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
|
|
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd
|
|
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd
|
|
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd
|
|
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de
|
|
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de
|
|
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
|
fsl,pins = <
|
|
/* Heart bit LED */
|
|
VF610_PAD_PTE12__GPIO_117 0x1183
|
|
/* LEDS */
|
|
VF610_PAD_PTE15__GPIO_120 0x1183
|
|
VF610_PAD_PTA12__GPIO_5 0x1183
|
|
VF610_PAD_PTA16__GPIO_6 0x1183
|
|
VF610_PAD_PTE9__GPIO_114 0x1183
|
|
VF610_PAD_PTE20__GPIO_125 0x1183
|
|
VF610_PAD_PTE23__GPIO_128 0x1183
|
|
VF610_PAD_PTE16__GPIO_121 0x1183
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_spi: pinctrl-gpio-spi {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB18__GPIO_40 0x1183
|
|
VF610_PAD_PTD10__GPIO_89 0x1183
|
|
VF610_PAD_PTD12__GPIO_91 0x1183
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA22__I2C2_SCL 0x34df
|
|
VF610_PAD_PTA23__I2C2_SDA 0x34df
|
|
>;
|
|
};
|
|
|
|
pinctrl_nfc: nfcgrp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD23__NF_IO7 0x28df
|
|
VF610_PAD_PTD22__NF_IO6 0x28df
|
|
VF610_PAD_PTD21__NF_IO5 0x28df
|
|
VF610_PAD_PTD20__NF_IO4 0x28df
|
|
VF610_PAD_PTD19__NF_IO3 0x28df
|
|
VF610_PAD_PTD18__NF_IO2 0x28df
|
|
VF610_PAD_PTD17__NF_IO1 0x28df
|
|
VF610_PAD_PTD16__NF_IO0 0x28df
|
|
VF610_PAD_PTB24__NF_WE_B 0x28c2
|
|
VF610_PAD_PTB25__NF_CE0_B 0x28c2
|
|
VF610_PAD_PTB27__NF_RE_B 0x28c2
|
|
VF610_PAD_PTC26__NF_RB_B 0x283d
|
|
VF610_PAD_PTC27__NF_ALE 0x28c2
|
|
VF610_PAD_PTC28__NF_CLE 0x28c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_qspi0: qspi0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f
|
|
VF610_PAD_PTD1__QSPI0_A_CS0 0x397f
|
|
VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f
|
|
VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f
|
|
VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f
|
|
VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f
|
|
VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f
|
|
VF610_PAD_PTD8__QSPI0_B_CS0 0x397f
|
|
VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f
|
|
VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart0: uart0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB10__UART0_TX 0x21a2
|
|
VF610_PAD_PTB11__UART0_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB4__UART1_TX 0x21a2
|
|
VF610_PAD_PTB5__UART1_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB6__UART2_TX 0x21a2
|
|
VF610_PAD_PTB7__UART2_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA20__UART3_TX 0x21a2
|
|
VF610_PAD_PTA21__UART3_RX 0x21a1
|
|
>;
|
|
};
|
|
};
|