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8d0d56ba24
linux/arch/arc/boot/dts
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Vineet Gupta 8d0d56ba24 ARC: [axs101] support early 8250 uart 
Earlycon calculates UART clock as "BASE_BAUD * 16". In case of ARC
"BASE_BAUD" is calculated dynamically in runtime, basically it is an
alias to arc_early_base_baud(), which in turn just does
"arc_base_baud/16".

8250 UART on AXS/SDP board uses 33.3MHz clock source which is set in
"arc_base_baud" with this change.

Additional compatibility string "snps,arc-sdp" is introduced as well
because there're different flavours of AXS boards but they all share the
same motherboard and so it's possible to re-use the same code for
motherbord even if CPU daughterboard changes.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:30 +05:30
..
abilis_tb10x.dtsi dmaengine: dw: define DW_DMA_MAX_NR_MASTERS 2015-02-04 22:39:44 -08:00
abilis_tb100_dvk.dts ARC: [TB10x] Updates for GPIO and pinctrl 2013-11-11 09:57:44 +05:30
abilis_tb100.dtsi ARC: [TB10x] Updates for GPIO and pinctrl 2013-11-11 09:57:44 +05:30
abilis_tb101_dvk.dts ARC: [TB10x] Updates for GPIO and pinctrl 2013-11-11 09:57:44 +05:30
abilis_tb101.dtsi ARC: [TB10x] Updates for GPIO and pinctrl 2013-11-11 09:57:44 +05:30
axc001.dtsi ARC: [axs101] Add support for AXS101 SDP (software development platform) 2015-06-19 18:09:30 +05:30
axs10x_mb.dtsi ARC: [axs101] Add support for AXS101 SDP (software development platform) 2015-06-19 18:09:30 +05:30
axs101.dts ARC: [axs101] support early 8250 uart 2015-06-19 18:09:30 +05:30
Makefile ARC: [plat_arcfpga]->[plat_sim] 2015-06-19 18:09:26 +05:30
nsim_700.dts ARC: [plat_arcfpga]->[plat_sim] 2015-06-19 18:09:26 +05:30
nsimosci.dts ARC: [nsimosci] move peripherals to match model to FPGA 2014-12-15 11:24:58 +05:30
skeleton.dtsi ARC: [plat-arcfpga]: Enabling DeviceTree for Angel4 board 2013-02-15 23:15:57 +05:30