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a855039ee4
This patch changes prefix of the clk register from S5P_ to EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix exynos4_ on clk declarations. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4210 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include "common.h"
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#include "clock-exynos4.h"
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#ifdef CONFIG_PM_SLEEP
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static struct sleep_save exynos4210_clock_save[] = {
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SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
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SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
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SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
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SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
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SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
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};
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#endif
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static struct clksrc_clk *sysclks[] = {
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/* nothing here yet */
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};
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static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
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}
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_sata",
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.id = -1,
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.enable = exynos4_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &exynos4_clkset_mout_corebus,
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.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimd",
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.devname = "exynos4-fb.1",
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.enable = exynos4_clksrc_mask_lcd1_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &exynos4_clkset_group,
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.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
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},
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};
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static struct clk init_clocks_off[] = {
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{
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.name = "sataphy",
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.id = -1,
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "sata",
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.id = -1,
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 10),
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}, {
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.name = "fimd",
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.devname = "exynos4-fb.1",
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 0),
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},
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4210_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
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return 0;
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}
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static void exynos4210_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
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}
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#else
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#define exynos4210_clock_suspend NULL
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#define exynos4210_clock_resume NULL
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#endif
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static struct syscore_ops exynos4210_clock_syscore_ops = {
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.suspend = exynos4210_clock_suspend,
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.resume = exynos4210_clock_resume,
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};
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void __init exynos4210_register_clocks(void)
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{
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int ptr;
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exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
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exynos4_clk_mout_mpll.reg_src.shift = 8;
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exynos4_clk_mout_mpll.reg_src.size = 1;
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for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
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s3c_register_clksrc(sysclks[ptr], 1);
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4210_clock_syscore_ops);
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}
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