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8c7849a302
Currently, a large part of the probe function runs before Runtime PM is
enabled. As the driver manages the device's clock manually, this may
work fine on some systems, but may break on platforms with a more
complex power hierarchy.
Fix this by moving the initialization of Runtime PM before the first
register access (in cc_wait_for_reset_completion()), and putting the
device to sleep only after the last access (in cc_set_ree_fips_status()).
This allows to remove the pm_on flag, which was used to track manually
if Runtime PM had been enabled or not.
Remove the cc_pm_{init,go,fini}() wrappers, as they are called only
once, and obscure operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
240 lines
6.3 KiB
C
240 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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/* \file cc_driver.h
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* ARM CryptoCell Linux Crypto Driver
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*/
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#ifndef __CC_DRIVER_H__
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#define __CC_DRIVER_H__
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#ifdef COMP_IN_WQ
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#include <linux/workqueue.h>
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#else
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#include <linux/interrupt.h>
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#endif
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#include <linux/dma-mapping.h>
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#include <crypto/algapi.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/aes.h>
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#include <crypto/sha.h>
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#include <crypto/aead.h>
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#include <crypto/authenc.h>
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#include <crypto/hash.h>
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#include <crypto/skcipher.h>
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#include <linux/version.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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/* Registers definitions from shared/hw/ree_include */
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#include "cc_host_regs.h"
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#include "cc_crypto_ctx.h"
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#include "cc_hw_queue_defs.h"
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#include "cc_sram_mgr.h"
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extern bool cc_dump_desc;
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extern bool cc_dump_bytes;
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#define DRV_MODULE_VERSION "5.0"
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enum cc_hw_rev {
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CC_HW_REV_630 = 630,
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CC_HW_REV_710 = 710,
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CC_HW_REV_712 = 712,
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CC_HW_REV_713 = 713
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};
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enum cc_std_body {
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CC_STD_NIST = 0x1,
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CC_STD_OSCCA = 0x2,
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CC_STD_ALL = 0x3
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};
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#define CC_COHERENT_CACHE_PARAMS 0xEEE
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#define CC_PINS_FULL 0x0
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#define CC_PINS_SLIM 0x9F
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/* Maximum DMA mask supported by IP */
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#define DMA_BIT_MASK_LEN 48
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#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
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(1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
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(1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
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(1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
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#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
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#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
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#define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
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#define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
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#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
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CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
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CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
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#define CC_CPP_AES_ABORT_MASK ( \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
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#define CC_CPP_SM4_ABORT_MASK ( \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
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/* Register name mangling macro */
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#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
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/* TEE FIPS status interrupt */
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#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
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#define CC_CRA_PRIO 400
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#define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
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#define MAX_REQUEST_QUEUE_SIZE 4096
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#define MAX_MLLI_BUFF_SIZE 2080
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/* Definitions for HW descriptors DIN/DOUT fields */
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#define NS_BIT 1
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#define AXI_ID 0
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/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
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* field in the HW descriptor. The DMA engine +8 that value.
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*/
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struct cc_cpp_req {
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bool is_cpp;
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enum cc_cpp_alg alg;
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u8 slot;
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};
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#define CC_MAX_IVGEN_DMA_ADDRESSES 3
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struct cc_crypto_req {
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void (*user_cb)(struct device *dev, void *req, int err);
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void *user_arg;
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struct completion seq_compl; /* request completion */
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struct cc_cpp_req cpp;
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};
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/**
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* struct cc_drvdata - driver private data context
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* @cc_base: virt address of the CC registers
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* @irq: bitmap indicating source of last interrupt
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*/
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struct cc_drvdata {
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void __iomem *cc_base;
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int irq;
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struct completion hw_queue_avail; /* wait for HW queue availability */
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struct platform_device *plat_dev;
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u32 mlli_sram_addr;
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void *buff_mgr_handle;
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void *cipher_handle;
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void *hash_handle;
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void *aead_handle;
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void *request_mgr_handle;
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void *fips_handle;
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void *sram_mgr_handle;
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void *debugfs;
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struct clk *clk;
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bool coherent;
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char *hw_rev_name;
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enum cc_hw_rev hw_rev;
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u32 axim_mon_offset;
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u32 sig_offset;
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u32 ver_offset;
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int std_bodies;
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bool sec_disabled;
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u32 comp_mask;
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};
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struct cc_crypto_alg {
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struct list_head entry;
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int cipher_mode;
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int flow_mode; /* Note: currently, refers to the cipher mode only. */
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int auth_mode;
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unsigned int data_unit;
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struct cc_drvdata *drvdata;
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struct skcipher_alg skcipher_alg;
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struct aead_alg aead_alg;
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};
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struct cc_alg_template {
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char name[CRYPTO_MAX_ALG_NAME];
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char driver_name[CRYPTO_MAX_ALG_NAME];
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unsigned int blocksize;
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union {
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struct skcipher_alg skcipher;
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struct aead_alg aead;
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} template_u;
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int cipher_mode;
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int flow_mode; /* Note: currently, refers to the cipher mode only. */
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int auth_mode;
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u32 min_hw_rev;
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enum cc_std_body std_body;
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bool sec_func;
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unsigned int data_unit;
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struct cc_drvdata *drvdata;
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};
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struct async_gen_req_ctx {
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dma_addr_t iv_dma_addr;
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u8 *iv;
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enum drv_crypto_direction op_type;
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};
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static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
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{
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return &drvdata->plat_dev->dev;
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}
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void __dump_byte_array(const char *name, const u8 *buf, size_t len);
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static inline void dump_byte_array(const char *name, const u8 *the_array,
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size_t size)
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{
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if (cc_dump_bytes)
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__dump_byte_array(name, the_array, size);
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}
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bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
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int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
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void fini_cc_regs(struct cc_drvdata *drvdata);
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unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
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static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
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{
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iowrite32(val, (drvdata->cc_base + reg));
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}
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static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
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{
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return ioread32(drvdata->cc_base + reg);
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}
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static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
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{
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return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
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GFP_KERNEL : GFP_ATOMIC;
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}
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static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
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struct cc_hw_desc *pdesc)
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{
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if (drvdata->hw_rev >= CC_HW_REV_712)
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set_queue_last_ind_bit(pdesc);
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}
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#endif /*__CC_DRIVER_H__*/
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