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973b9e3733
If FEAT_MTE2 is disabled via the arm64.nomte command line argument on a
CPU that claims to support FEAT_MTE2, the kernel will use Tagged Normal
in the MAIR. If we interpret arm64.nomte to mean that the CPU does not
in fact implement FEAT_MTE2, setting the system register like this may
lead to UNSPECIFIED behavior. Fix it by arranging for MAIR to be set
in the C function cpu_enable_mte which is called based on the sanitized
version of the system register.
There is no need for the rest of the MTE-related system register
initialization to happen from assembly, with the exception of TCR_EL1,
which must be set to include at least TBI1 because the secondary CPUs
access KASan-allocated data structures early. Therefore, make the TCR_EL1
initialization unconditional and move the rest of the initialization to
cpu_enable_mte so that we no longer have a dependency on the unsanitized
ID register value.
Co-developed-by: Evgenii Stepanov <eugenis@google.com>
Signed-off-by: Peter Collingbourne <pcc@google.com>
Signed-off-by: Evgenii Stepanov <eugenis@google.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b714d24ef
("arm64: mte: CPU feature detection and initial sysreg configuration")
Cc: <stable@vger.kernel.org> # 5.10.x
Link: https://lore.kernel.org/r/20220915222053.3484231-1-eugenis@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
628 lines
16 KiB
C
628 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 ARM Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/cpu.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/prctl.h>
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#include <linux/sched.h>
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#include <linux/sched/mm.h>
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#include <linux/string.h>
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#include <linux/swap.h>
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#include <linux/swapops.h>
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#include <linux/thread_info.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <linux/uio.h>
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#include <asm/barrier.h>
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#include <asm/cpufeature.h>
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#include <asm/mte.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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static DEFINE_PER_CPU_READ_MOSTLY(u64, mte_tcf_preferred);
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#ifdef CONFIG_KASAN_HW_TAGS
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/*
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* The asynchronous and asymmetric MTE modes have the same behavior for
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* store operations. This flag is set when either of these modes is enabled.
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*/
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DEFINE_STATIC_KEY_FALSE(mte_async_or_asymm_mode);
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EXPORT_SYMBOL_GPL(mte_async_or_asymm_mode);
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#endif
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static void mte_sync_page_tags(struct page *page, pte_t old_pte,
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bool check_swap, bool pte_is_tagged)
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{
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if (check_swap && is_swap_pte(old_pte)) {
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swp_entry_t entry = pte_to_swp_entry(old_pte);
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if (!non_swap_entry(entry) && mte_restore_tags(entry, page))
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return;
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}
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if (!pte_is_tagged)
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return;
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mte_clear_page_tags(page_address(page));
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}
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void mte_sync_tags(pte_t old_pte, pte_t pte)
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{
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struct page *page = pte_page(pte);
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long i, nr_pages = compound_nr(page);
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bool check_swap = nr_pages == 1;
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bool pte_is_tagged = pte_tagged(pte);
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/* Early out if there's nothing to do */
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if (!check_swap && !pte_is_tagged)
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return;
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/* if PG_mte_tagged is set, tags have already been initialised */
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for (i = 0; i < nr_pages; i++, page++) {
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if (!test_and_set_bit(PG_mte_tagged, &page->flags))
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mte_sync_page_tags(page, old_pte, check_swap,
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pte_is_tagged);
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}
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/* ensure the tags are visible before the PTE is set */
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smp_wmb();
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}
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int memcmp_pages(struct page *page1, struct page *page2)
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{
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char *addr1, *addr2;
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int ret;
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addr1 = page_address(page1);
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addr2 = page_address(page2);
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ret = memcmp(addr1, addr2, PAGE_SIZE);
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if (!system_supports_mte() || ret)
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return ret;
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/*
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* If the page content is identical but at least one of the pages is
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* tagged, return non-zero to avoid KSM merging. If only one of the
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* pages is tagged, set_pte_at() may zero or change the tags of the
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* other page via mte_sync_tags().
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*/
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if (test_bit(PG_mte_tagged, &page1->flags) ||
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test_bit(PG_mte_tagged, &page2->flags))
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return addr1 != addr2;
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return ret;
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}
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static inline void __mte_enable_kernel(const char *mode, unsigned long tcf)
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{
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/* Enable MTE Sync Mode for EL1. */
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK,
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SYS_FIELD_PREP(SCTLR_EL1, TCF, tcf));
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isb();
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pr_info_once("MTE: enabled in %s mode at EL1\n", mode);
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}
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#ifdef CONFIG_KASAN_HW_TAGS
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void mte_enable_kernel_sync(void)
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{
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/*
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* Make sure we enter this function when no PE has set
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* async mode previously.
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*/
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WARN_ONCE(system_uses_mte_async_or_asymm_mode(),
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"MTE async mode enabled system wide!");
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__mte_enable_kernel("synchronous", SCTLR_EL1_TCF_SYNC);
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}
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void mte_enable_kernel_async(void)
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{
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__mte_enable_kernel("asynchronous", SCTLR_EL1_TCF_ASYNC);
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/*
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* MTE async mode is set system wide by the first PE that
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* executes this function.
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*
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* Note: If in future KASAN acquires a runtime switching
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* mode in between sync and async, this strategy needs
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* to be reviewed.
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*/
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if (!system_uses_mte_async_or_asymm_mode())
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static_branch_enable(&mte_async_or_asymm_mode);
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}
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void mte_enable_kernel_asymm(void)
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{
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if (cpus_have_cap(ARM64_MTE_ASYMM)) {
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__mte_enable_kernel("asymmetric", SCTLR_EL1_TCF_ASYMM);
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/*
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* MTE asymm mode behaves as async mode for store
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* operations. The mode is set system wide by the
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* first PE that executes this function.
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*
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* Note: If in future KASAN acquires a runtime switching
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* mode in between sync and async, this strategy needs
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* to be reviewed.
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*/
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if (!system_uses_mte_async_or_asymm_mode())
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static_branch_enable(&mte_async_or_asymm_mode);
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} else {
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/*
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* If the CPU does not support MTE asymmetric mode the
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* kernel falls back on synchronous mode which is the
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* default for kasan=on.
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*/
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mte_enable_kernel_sync();
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}
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}
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#endif
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#ifdef CONFIG_KASAN_HW_TAGS
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void mte_check_tfsr_el1(void)
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{
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u64 tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
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if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) {
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/*
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* Note: isb() is not required after this direct write
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* because there is no indirect read subsequent to it
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* (per ARM DDI 0487F.c table D13-1).
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*/
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write_sysreg_s(0, SYS_TFSR_EL1);
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kasan_report_async();
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}
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}
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#endif
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/*
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* This is where we actually resolve the system and process MTE mode
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* configuration into an actual value in SCTLR_EL1 that affects
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* userspace.
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*/
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static void mte_update_sctlr_user(struct task_struct *task)
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{
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/*
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* This must be called with preemption disabled and can only be called
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* on the current or next task since the CPU must match where the thread
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* is going to run. The caller is responsible for calling
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* update_sctlr_el1() later in the same preemption disabled block.
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*/
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unsigned long sctlr = task->thread.sctlr_user;
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unsigned long mte_ctrl = task->thread.mte_ctrl;
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unsigned long pref, resolved_mte_tcf;
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pref = __this_cpu_read(mte_tcf_preferred);
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/*
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* If there is no overlap between the system preferred and
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* program requested values go with what was requested.
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*/
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resolved_mte_tcf = (mte_ctrl & pref) ? pref : mte_ctrl;
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sctlr &= ~SCTLR_EL1_TCF0_MASK;
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/*
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* Pick an actual setting. The order in which we check for
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* set bits and map into register values determines our
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* default order.
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*/
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if (resolved_mte_tcf & MTE_CTRL_TCF_ASYMM)
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sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYMM);
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else if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC)
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sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYNC);
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else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC)
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sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, SYNC);
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task->thread.sctlr_user = sctlr;
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}
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static void mte_update_gcr_excl(struct task_struct *task)
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{
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/*
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* SYS_GCR_EL1 will be set to current->thread.mte_ctrl value by
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* mte_set_user_gcr() in kernel_exit, but only if KASAN is enabled.
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*/
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if (kasan_hw_tags_enabled())
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return;
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write_sysreg_s(
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((task->thread.mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
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SYS_GCR_EL1_EXCL_MASK) | SYS_GCR_EL1_RRND,
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SYS_GCR_EL1);
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}
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#ifdef CONFIG_KASAN_HW_TAGS
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/* Only called from assembly, silence sparse */
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void __init kasan_hw_tags_enable(struct alt_instr *alt, __le32 *origptr,
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__le32 *updptr, int nr_inst);
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void __init kasan_hw_tags_enable(struct alt_instr *alt, __le32 *origptr,
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__le32 *updptr, int nr_inst)
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{
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BUG_ON(nr_inst != 1); /* Branch -> NOP */
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if (kasan_hw_tags_enabled())
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*updptr = cpu_to_le32(aarch64_insn_gen_nop());
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}
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#endif
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void mte_thread_init_user(void)
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{
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if (!system_supports_mte())
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return;
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/* clear any pending asynchronous tag fault */
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dsb(ish);
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write_sysreg_s(0, SYS_TFSRE0_EL1);
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clear_thread_flag(TIF_MTE_ASYNC_FAULT);
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/* disable tag checking and reset tag generation mask */
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set_mte_ctrl(current, 0);
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}
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void mte_thread_switch(struct task_struct *next)
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{
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if (!system_supports_mte())
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return;
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mte_update_sctlr_user(next);
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mte_update_gcr_excl(next);
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/* TCO may not have been disabled on exception entry for the current task. */
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mte_disable_tco_entry(next);
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/*
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* Check if an async tag exception occurred at EL1.
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*
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* Note: On the context switch path we rely on the dsb() present
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* in __switch_to() to guarantee that the indirect writes to TFSR_EL1
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* are synchronized before this point.
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*/
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isb();
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mte_check_tfsr_el1();
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}
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void mte_cpu_setup(void)
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{
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u64 rgsr;
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/*
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* CnP must be enabled only after the MAIR_EL1 register has been set
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* up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may
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* lead to the wrong memory type being used for a brief window during
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* CPU power-up.
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*
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* CnP is not a boot feature so MTE gets enabled before CnP, but let's
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* make sure that is the case.
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*/
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BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT);
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BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT);
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/* Normal Tagged memory type at the corresponding MAIR index */
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sysreg_clear_set(mair_el1,
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MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED),
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL_TAGGED,
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MT_NORMAL_TAGGED));
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write_sysreg_s(KERNEL_GCR_EL1, SYS_GCR_EL1);
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/*
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* If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
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* RGSR_EL1.SEED must be non-zero for IRG to produce
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* pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
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* must initialize it.
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*/
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rgsr = (read_sysreg(CNTVCT_EL0) & SYS_RGSR_EL1_SEED_MASK) <<
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SYS_RGSR_EL1_SEED_SHIFT;
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if (rgsr == 0)
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rgsr = 1 << SYS_RGSR_EL1_SEED_SHIFT;
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write_sysreg_s(rgsr, SYS_RGSR_EL1);
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/* clear any pending tag check faults in TFSR*_EL1 */
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write_sysreg_s(0, SYS_TFSR_EL1);
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write_sysreg_s(0, SYS_TFSRE0_EL1);
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local_flush_tlb_all();
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}
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void mte_suspend_enter(void)
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{
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if (!system_supports_mte())
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return;
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/*
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* The barriers are required to guarantee that the indirect writes
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* to TFSR_EL1 are synchronized before we report the state.
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*/
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dsb(nsh);
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isb();
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/* Report SYS_TFSR_EL1 before suspend entry */
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mte_check_tfsr_el1();
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}
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void mte_suspend_exit(void)
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{
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if (!system_supports_mte())
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return;
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mte_cpu_setup();
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}
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long set_mte_ctrl(struct task_struct *task, unsigned long arg)
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{
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u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
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SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT;
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if (!system_supports_mte())
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return 0;
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if (arg & PR_MTE_TCF_ASYNC)
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mte_ctrl |= MTE_CTRL_TCF_ASYNC;
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if (arg & PR_MTE_TCF_SYNC)
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mte_ctrl |= MTE_CTRL_TCF_SYNC;
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/*
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* If the system supports it and both sync and async modes are
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* specified then implicitly enable asymmetric mode.
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* Userspace could see a mix of both sync and async anyway due
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* to differing or changing defaults on CPUs.
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*/
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if (cpus_have_cap(ARM64_MTE_ASYMM) &&
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(arg & PR_MTE_TCF_ASYNC) &&
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(arg & PR_MTE_TCF_SYNC))
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mte_ctrl |= MTE_CTRL_TCF_ASYMM;
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task->thread.mte_ctrl = mte_ctrl;
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if (task == current) {
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preempt_disable();
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mte_update_sctlr_user(task);
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mte_update_gcr_excl(task);
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update_sctlr_el1(task->thread.sctlr_user);
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preempt_enable();
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}
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return 0;
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}
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long get_mte_ctrl(struct task_struct *task)
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{
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unsigned long ret;
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u64 mte_ctrl = task->thread.mte_ctrl;
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u64 incl = (~mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
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SYS_GCR_EL1_EXCL_MASK;
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if (!system_supports_mte())
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return 0;
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ret = incl << PR_MTE_TAG_SHIFT;
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if (mte_ctrl & MTE_CTRL_TCF_ASYNC)
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ret |= PR_MTE_TCF_ASYNC;
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if (mte_ctrl & MTE_CTRL_TCF_SYNC)
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ret |= PR_MTE_TCF_SYNC;
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return ret;
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}
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/*
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* Access MTE tags in another process' address space as given in mm. Update
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* the number of tags copied. Return 0 if any tags copied, error otherwise.
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* Inspired by __access_remote_vm().
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*/
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static int __access_remote_tags(struct mm_struct *mm, unsigned long addr,
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struct iovec *kiov, unsigned int gup_flags)
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{
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struct vm_area_struct *vma;
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void __user *buf = kiov->iov_base;
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size_t len = kiov->iov_len;
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int ret;
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int write = gup_flags & FOLL_WRITE;
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if (!access_ok(buf, len))
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return -EFAULT;
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if (mmap_read_lock_killable(mm))
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return -EIO;
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while (len) {
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unsigned long tags, offset;
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void *maddr;
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struct page *page = NULL;
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ret = get_user_pages_remote(mm, addr, 1, gup_flags, &page,
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&vma, NULL);
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if (ret <= 0)
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break;
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/*
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* Only copy tags if the page has been mapped as PROT_MTE
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* (PG_mte_tagged set). Otherwise the tags are not valid and
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* not accessible to user. Moreover, an mprotect(PROT_MTE)
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* would cause the existing tags to be cleared if the page
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* was never mapped with PROT_MTE.
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*/
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if (!(vma->vm_flags & VM_MTE)) {
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ret = -EOPNOTSUPP;
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put_page(page);
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break;
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}
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WARN_ON_ONCE(!test_bit(PG_mte_tagged, &page->flags));
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/* limit access to the end of the page */
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offset = offset_in_page(addr);
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tags = min(len, (PAGE_SIZE - offset) / MTE_GRANULE_SIZE);
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maddr = page_address(page);
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if (write) {
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tags = mte_copy_tags_from_user(maddr + offset, buf, tags);
|
|
set_page_dirty_lock(page);
|
|
} else {
|
|
tags = mte_copy_tags_to_user(buf, maddr + offset, tags);
|
|
}
|
|
put_page(page);
|
|
|
|
/* error accessing the tracer's buffer */
|
|
if (!tags)
|
|
break;
|
|
|
|
len -= tags;
|
|
buf += tags;
|
|
addr += tags * MTE_GRANULE_SIZE;
|
|
}
|
|
mmap_read_unlock(mm);
|
|
|
|
/* return an error if no tags copied */
|
|
kiov->iov_len = buf - kiov->iov_base;
|
|
if (!kiov->iov_len) {
|
|
/* check for error accessing the tracee's address space */
|
|
if (ret <= 0)
|
|
return -EIO;
|
|
else
|
|
return -EFAULT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Copy MTE tags in another process' address space at 'addr' to/from tracer's
|
|
* iovec buffer. Return 0 on success. Inspired by ptrace_access_vm().
|
|
*/
|
|
static int access_remote_tags(struct task_struct *tsk, unsigned long addr,
|
|
struct iovec *kiov, unsigned int gup_flags)
|
|
{
|
|
struct mm_struct *mm;
|
|
int ret;
|
|
|
|
mm = get_task_mm(tsk);
|
|
if (!mm)
|
|
return -EPERM;
|
|
|
|
if (!tsk->ptrace || (current != tsk->parent) ||
|
|
((get_dumpable(mm) != SUID_DUMP_USER) &&
|
|
!ptracer_capable(tsk, mm->user_ns))) {
|
|
mmput(mm);
|
|
return -EPERM;
|
|
}
|
|
|
|
ret = __access_remote_tags(mm, addr, kiov, gup_flags);
|
|
mmput(mm);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int mte_ptrace_copy_tags(struct task_struct *child, long request,
|
|
unsigned long addr, unsigned long data)
|
|
{
|
|
int ret;
|
|
struct iovec kiov;
|
|
struct iovec __user *uiov = (void __user *)data;
|
|
unsigned int gup_flags = FOLL_FORCE;
|
|
|
|
if (!system_supports_mte())
|
|
return -EIO;
|
|
|
|
if (get_user(kiov.iov_base, &uiov->iov_base) ||
|
|
get_user(kiov.iov_len, &uiov->iov_len))
|
|
return -EFAULT;
|
|
|
|
if (request == PTRACE_POKEMTETAGS)
|
|
gup_flags |= FOLL_WRITE;
|
|
|
|
/* align addr to the MTE tag granule */
|
|
addr &= MTE_GRANULE_MASK;
|
|
|
|
ret = access_remote_tags(child, addr, &kiov, gup_flags);
|
|
if (!ret)
|
|
ret = put_user(kiov.iov_len, &uiov->iov_len);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t mte_tcf_preferred_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
switch (per_cpu(mte_tcf_preferred, dev->id)) {
|
|
case MTE_CTRL_TCF_ASYNC:
|
|
return sysfs_emit(buf, "async\n");
|
|
case MTE_CTRL_TCF_SYNC:
|
|
return sysfs_emit(buf, "sync\n");
|
|
case MTE_CTRL_TCF_ASYMM:
|
|
return sysfs_emit(buf, "asymm\n");
|
|
default:
|
|
return sysfs_emit(buf, "???\n");
|
|
}
|
|
}
|
|
|
|
static ssize_t mte_tcf_preferred_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
u64 tcf;
|
|
|
|
if (sysfs_streq(buf, "async"))
|
|
tcf = MTE_CTRL_TCF_ASYNC;
|
|
else if (sysfs_streq(buf, "sync"))
|
|
tcf = MTE_CTRL_TCF_SYNC;
|
|
else if (cpus_have_cap(ARM64_MTE_ASYMM) && sysfs_streq(buf, "asymm"))
|
|
tcf = MTE_CTRL_TCF_ASYMM;
|
|
else
|
|
return -EINVAL;
|
|
|
|
device_lock(dev);
|
|
per_cpu(mte_tcf_preferred, dev->id) = tcf;
|
|
device_unlock(dev);
|
|
|
|
return count;
|
|
}
|
|
static DEVICE_ATTR_RW(mte_tcf_preferred);
|
|
|
|
static int register_mte_tcf_preferred_sysctl(void)
|
|
{
|
|
unsigned int cpu;
|
|
|
|
if (!system_supports_mte())
|
|
return 0;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
per_cpu(mte_tcf_preferred, cpu) = MTE_CTRL_TCF_ASYNC;
|
|
device_create_file(get_cpu_device(cpu),
|
|
&dev_attr_mte_tcf_preferred);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(register_mte_tcf_preferred_sysctl);
|
|
|
|
/*
|
|
* Return 0 on success, the number of bytes not probed otherwise.
|
|
*/
|
|
size_t mte_probe_user_range(const char __user *uaddr, size_t size)
|
|
{
|
|
const char __user *end = uaddr + size;
|
|
int err = 0;
|
|
char val;
|
|
|
|
__raw_get_user(val, uaddr, err);
|
|
if (err)
|
|
return size;
|
|
|
|
uaddr = PTR_ALIGN(uaddr, MTE_GRANULE_SIZE);
|
|
while (uaddr < end) {
|
|
/*
|
|
* A read is sufficient for mte, the caller should have probed
|
|
* for the pte write permission if required.
|
|
*/
|
|
__raw_get_user(val, uaddr, err);
|
|
if (err)
|
|
return end - uaddr;
|
|
uaddr += MTE_GRANULE_SIZE;
|
|
}
|
|
(void)val;
|
|
|
|
return 0;
|
|
}
|